<feed xmlns='http://www.w3.org/2005/Atom'>
<title>bwlp/qemu.git/configs/targets, branch master</title>
<subtitle>Experimental fork of QEMU with video encoding patches</subtitle>
<id>https://git.openslx.org/bwlp/qemu.git/atom/configs/targets?h=master</id>
<link rel='self' href='https://git.openslx.org/bwlp/qemu.git/atom/configs/targets?h=master'/>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/'/>
<updated>2022-09-04T06:02:57+00:00</updated>
<entry>
<title>target/openrisc: Enable MTTCG</title>
<updated>2022-09-04T06:02:57+00:00</updated>
<author>
<name>Stafford Horne</name>
</author>
<published>2022-06-14T23:43:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=6a0fc96ad2b16a264ead6b696bdb91a963450dbb'/>
<id>urn:sha1:6a0fc96ad2b16a264ead6b696bdb91a963450dbb</id>
<content type='text'>
This patch enables multithread TCG for OpenRISC.  Since the or1k shared
syncrhonized timer can be updated from each vCPU via helpers we use a
mutex to synchronize updates.

Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</content>
</entry>
<entry>
<title>target/loongarch: Update loongarch-fpu.xml</title>
<updated>2022-08-05T17:02:40+00:00</updated>
<author>
<name>Song Gao</name>
</author>
<published>2022-08-05T03:35:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=d182c3900072ea9b7f4de8785b441a2aa4804d48'/>
<id>urn:sha1:d182c3900072ea9b7f4de8785b441a2aa4804d48</id>
<content type='text'>
Rename loongarch-fpu64.xml to loongarch-fpu.xml and update
loongarch-fpu.xml to match upstream GDB [1]

[1]:https://github.com/bminor/binutils-gdb/blob/master/gdb/features/loongarch/fpu.xml

Signed-off-by: Song Gao &lt;gaosong@loongson.cn&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Acked-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Message-Id: &lt;20220805033523.1416837-5-gaosong@loongson.cn&gt;
</content>
</entry>
<entry>
<title>hw/loongarch: Add fdt support</title>
<updated>2022-07-19T17:25:10+00:00</updated>
<author>
<name>Xiaojuan Yang</name>
</author>
<published>2022-07-12T08:32:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=fda3f15b0079d4bba76791502a7e00b8b747f509'/>
<id>urn:sha1:fda3f15b0079d4bba76791502a7e00b8b747f509</id>
<content type='text'>
Add LoongArch flatted device tree, adding cpu device node, firmware cfg node,
pcie node into it, and create fdt rom memory region. Now fdt info is not
full since only uefi bios uses fdt, linux kernel does not use fdt.
Loongarch Linux kernel uses acpi table which is full in qemu virt
machine.

Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Signed-off-by: Xiaojuan Yang &lt;yangxiaojuan@loongson.cn&gt;
Message-Id: &lt;20220712083206.4187715-7-yangxiaojuan@loongson.cn&gt;
[rth: Set TARGET_NEED_FDT, add fdt to meson.build]
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>default-configs: Add loongarch linux-user support</title>
<updated>2022-07-04T05:38:58+00:00</updated>
<author>
<name>Song Gao</name>
</author>
<published>2022-06-24T03:10:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=d32688ecdb43c9a22fc87d0c3e23aed5d15e3b02'/>
<id>urn:sha1:d32688ecdb43c9a22fc87d0c3e23aed5d15e3b02</id>
<content type='text'>
This patch adds loongarch64 linux-user default configs file.

Signed-off-by: Song Gao &lt;gaosong@loongson.cn&gt;
Signed-off-by: Xiaojuan Yang &lt;yangxiaojuan@loongson.cn&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Reviewed-by: WANG Xuerui &lt;git@xen0n.name&gt;
Message-Id: &lt;20220624031049.1716097-13-gaosong@loongson.cn&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>semihosting: Split out guestfd.c</title>
<updated>2022-06-27T23:05:07+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-04-28T04:38:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=1c6ff7205bff49870dc3511f237b3ad90da5f5f7'/>
<id>urn:sha1:1c6ff7205bff49870dc3511f237b3ad90da5f5f7</id>
<content type='text'>
In arm-compat-semi.c, we have more advanced treatment of
guest file descriptors than we do in other implementations.
Split out GuestFD and related functions to a new file so
that they can be shared.

Reviewed-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Reviewed-by: Peter Maydell &lt;peter.maydell@linaro.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>target/loongarch: Add gdb support.</title>
<updated>2022-06-06T18:14:13+00:00</updated>
<author>
<name>Xiaojuan Yang</name>
</author>
<published>2022-06-06T12:43:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=ca61e75071c647cf93b3161a228c6a54178cd58c'/>
<id>urn:sha1:ca61e75071c647cf93b3161a228c6a54178cd58c</id>
<content type='text'>
Signed-off-by: Xiaojuan Yang &lt;yangxiaojuan@loongson.cn&gt;
Signed-off-by: Song Gao &lt;gaosong@loongson.cn&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-Id: &lt;20220606124333.2060567-42-yangxiaojuan@loongson.cn&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>hw/loongarch: Add support loongson3 virt machine type.</title>
<updated>2022-06-06T18:09:03+00:00</updated>
<author>
<name>Xiaojuan Yang</name>
</author>
<published>2022-06-06T12:43:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=a8a506c3907093a064dd2d475564e677fb1bf148'/>
<id>urn:sha1:a8a506c3907093a064dd2d475564e677fb1bf148</id>
<content type='text'>
Emulate a 3A5000 board use the new loongarch instruction.
3A5000 belongs to the Loongson3 series processors.
The board consists of a 3A5000 cpu model and the virt
bridge. The host 3A5000 board is really complicated and
contains many functions.Now for the tcg softmmu mode
only part functions are emulated.

More detailed info you can see
https://github.com/loongson/LoongArch-Documentation

Signed-off-by: Xiaojuan Yang &lt;yangxiaojuan@loongson.cn&gt;
Signed-off-by: Song Gao &lt;gaosong@loongson.cn&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-Id: &lt;20220606124333.2060567-31-yangxiaojuan@loongson.cn&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>target/nios2: Enable unaligned traps for system mode</title>
<updated>2022-04-26T15:17:05+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-04-21T15:17:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=0706ac0f860896a73299cb4d2de50a9216e2f5bb'/>
<id>urn:sha1:0706ac0f860896a73299cb4d2de50a9216e2f5bb</id>
<content type='text'>
Unaligned traps are optional, but required with an mmu.
Turn them on always, because the fallback behaviour undefined.

Enable alignment checks in the config file.
Unwind the guest pc properly from do_unaligned_access.

Reviewed-by: Peter Maydell &lt;peter.maydell@linaro.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-Id: &lt;20220421151735.31996-48-richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>Replace TARGET_WORDS_BIGENDIAN</title>
<updated>2022-04-06T08:50:37+00:00</updated>
<author>
<name>Marc-André Lureau</name>
</author>
<published>2022-03-23T15:57:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=ee3eb3a7ce7242735e6fd64cad53482e3df5a5ec'/>
<id>urn:sha1:ee3eb3a7ce7242735e6fd64cad53482e3df5a5ec</id>
<content type='text'>
Convert the TARGET_WORDS_BIGENDIAN macro, similarly to what was done
with HOST_BIG_ENDIAN. The new TARGET_BIG_ENDIAN macro is either 0 or 1,
and thus should always be defined to prevent misuse.

Signed-off-by: Marc-André Lureau &lt;marcandre.lureau@redhat.com&gt;
Suggested-by: Halil Pasic &lt;pasic@linux.ibm.com&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-Id: &lt;20220323155743.1585078-8-marcandre.lureau@redhat.com&gt;
Signed-off-by: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
</content>
</entry>
<entry>
<title>hw/openrisc/openrisc_sim: Add automatic device tree generation</title>
<updated>2022-02-26T01:39:36+00:00</updated>
<author>
<name>Stafford Horne</name>
</author>
<published>2022-02-09T21:39:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=5852c1f86529ca6f4055a69d1683f91384fceaed'/>
<id>urn:sha1:5852c1f86529ca6f4055a69d1683f91384fceaed</id>
<content type='text'>
Using the device tree means that qemu can now directly tell
the kernel what hardware is configured rather than use having
to maintain and update a separate device tree file.

This patch adds automatic device tree generation support for the
OpenRISC simulator.  A device tree is built up based on the state of the
configure openrisc simulator.

This is then dumped to memory and the load address is passed to the
kernel in register r3.

Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
Reviewed-by: Peter Maydell &lt;peter.maydell@linaro.org&gt;
</content>
</entry>
</feed>
