<feed xmlns='http://www.w3.org/2005/Atom'>
<title>bwlp/qemu.git/configs, branch spice_video_codecs</title>
<subtitle>Experimental fork of QEMU with video encoding patches</subtitle>
<id>https://git.openslx.org/bwlp/qemu.git/atom/configs?h=spice_video_codecs</id>
<link rel='self' href='https://git.openslx.org/bwlp/qemu.git/atom/configs?h=spice_video_codecs'/>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/'/>
<updated>2022-10-31T10:32:07+00:00</updated>
<entry>
<title>hw/isa/Kconfig: Fix dependencies of piix4 southbridge</title>
<updated>2022-10-31T10:32:07+00:00</updated>
<author>
<name>Bernhard Beschow</name>
</author>
<published>2022-10-22T15:04:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=195f7e77de374b6b9776be3bbbc71c7a11ae5622'/>
<id>urn:sha1:195f7e77de374b6b9776be3bbbc71c7a11ae5622</id>
<content type='text'>
Signed-off-by: Bernhard Beschow &lt;shentey@gmail.com&gt;
Message-Id: &lt;20221022150508.26830-27-shentey@gmail.com&gt;
Signed-off-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
</content>
</entry>
<entry>
<title>hw/isa/vt82c686: Instantiate IDE function in host device</title>
<updated>2022-10-31T10:32:07+00:00</updated>
<author>
<name>Bernhard Beschow</name>
</author>
<published>2022-06-13T17:24:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=9eb6abbf6aea3116b3a4a7a6fbbb89ec836c0551'/>
<id>urn:sha1:9eb6abbf6aea3116b3a4a7a6fbbb89ec836c0551</id>
<content type='text'>
The IDE function is closely tied to the ISA function (e.g. the IDE
interrupt routing happens there), so it makes sense that the IDE
function is instantiated within the south bridge itself.

Signed-off-by: Bernhard Beschow &lt;shentey@gmail.com&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Acked-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
Message-Id: &lt;20220901114127.53914-7-shentey@gmail.com&gt;
Signed-off-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
</content>
</entry>
<entry>
<title>hw/ppc/meson: Allow e500 boards to be enabled separately</title>
<updated>2022-10-17T19:15:09+00:00</updated>
<author>
<name>Bernhard Beschow</name>
</author>
<published>2022-10-03T20:31:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=8cf7b3277d705976a6c9dce90b481824cf8f10ff'/>
<id>urn:sha1:8cf7b3277d705976a6c9dce90b481824cf8f10ff</id>
<content type='text'>
Gives users more fine-grained control over what should be compiled into
QEMU.

Signed-off-by: Bernhard Beschow &lt;shentey@gmail.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Message-Id: &lt;20221003203142.24355-2-shentey@gmail.com&gt;
Signed-off-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
</content>
</entry>
<entry>
<title>target/openrisc: Enable MTTCG</title>
<updated>2022-09-04T06:02:57+00:00</updated>
<author>
<name>Stafford Horne</name>
</author>
<published>2022-06-14T23:43:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=6a0fc96ad2b16a264ead6b696bdb91a963450dbb'/>
<id>urn:sha1:6a0fc96ad2b16a264ead6b696bdb91a963450dbb</id>
<content type='text'>
This patch enables multithread TCG for OpenRISC.  Since the or1k shared
syncrhonized timer can be updated from each vCPU via helpers we use a
mutex to synchronize updates.

Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</content>
</entry>
<entry>
<title>hw/openrisc: Add the OpenRISC virtual machine</title>
<updated>2022-09-04T06:02:57+00:00</updated>
<author>
<name>Stafford Horne</name>
</author>
<published>2022-05-20T13:38:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=b5fcfe927b7a9cbbc0864e7fc4f34bc94631ee0e'/>
<id>urn:sha1:b5fcfe927b7a9cbbc0864e7fc4f34bc94631ee0e</id>
<content type='text'>
This patch adds the OpenRISC virtual machine 'virt' for OpenRISC.  This
platform allows for a convenient CI platform for toolchain, software
ports and the OpenRISC linux kernel port.

Much of this has been sourced from the m68k and riscv virt platforms.

The platform provides:
 - OpenRISC SMP with up to 4 cpus
 - A virtio bus with up to 8 devices
 - Standard ns16550a serial
 - Goldfish RTC
 - SiFive TEST device for poweroff and reboot
 - Generated Device Tree to automatically configure the guest kernel

Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</content>
</entry>
<entry>
<title>target/loongarch: Update loongarch-fpu.xml</title>
<updated>2022-08-05T17:02:40+00:00</updated>
<author>
<name>Song Gao</name>
</author>
<published>2022-08-05T03:35:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=d182c3900072ea9b7f4de8785b441a2aa4804d48'/>
<id>urn:sha1:d182c3900072ea9b7f4de8785b441a2aa4804d48</id>
<content type='text'>
Rename loongarch-fpu64.xml to loongarch-fpu.xml and update
loongarch-fpu.xml to match upstream GDB [1]

[1]:https://github.com/bminor/binutils-gdb/blob/master/gdb/features/loongarch/fpu.xml

Signed-off-by: Song Gao &lt;gaosong@loongson.cn&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Acked-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Message-Id: &lt;20220805033523.1416837-5-gaosong@loongson.cn&gt;
</content>
</entry>
<entry>
<title>hw/loongarch: Add fdt support</title>
<updated>2022-07-19T17:25:10+00:00</updated>
<author>
<name>Xiaojuan Yang</name>
</author>
<published>2022-07-12T08:32:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=fda3f15b0079d4bba76791502a7e00b8b747f509'/>
<id>urn:sha1:fda3f15b0079d4bba76791502a7e00b8b747f509</id>
<content type='text'>
Add LoongArch flatted device tree, adding cpu device node, firmware cfg node,
pcie node into it, and create fdt rom memory region. Now fdt info is not
full since only uefi bios uses fdt, linux kernel does not use fdt.
Loongarch Linux kernel uses acpi table which is full in qemu virt
machine.

Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Signed-off-by: Xiaojuan Yang &lt;yangxiaojuan@loongson.cn&gt;
Message-Id: &lt;20220712083206.4187715-7-yangxiaojuan@loongson.cn&gt;
[rth: Set TARGET_NEED_FDT, add fdt to meson.build]
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>default-configs: Add loongarch linux-user support</title>
<updated>2022-07-04T05:38:58+00:00</updated>
<author>
<name>Song Gao</name>
</author>
<published>2022-06-24T03:10:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=d32688ecdb43c9a22fc87d0c3e23aed5d15e3b02'/>
<id>urn:sha1:d32688ecdb43c9a22fc87d0c3e23aed5d15e3b02</id>
<content type='text'>
This patch adds loongarch64 linux-user default configs file.

Signed-off-by: Song Gao &lt;gaosong@loongson.cn&gt;
Signed-off-by: Xiaojuan Yang &lt;yangxiaojuan@loongson.cn&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Reviewed-by: WANG Xuerui &lt;git@xen0n.name&gt;
Message-Id: &lt;20220624031049.1716097-13-gaosong@loongson.cn&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>semihosting: Split out guestfd.c</title>
<updated>2022-06-27T23:05:07+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-04-28T04:38:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=1c6ff7205bff49870dc3511f237b3ad90da5f5f7'/>
<id>urn:sha1:1c6ff7205bff49870dc3511f237b3ad90da5f5f7</id>
<content type='text'>
In arm-compat-semi.c, we have more advanced treatment of
guest file descriptors than we do in other implementations.
Split out GuestFD and related functions to a new file so
that they can be shared.

Reviewed-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Reviewed-by: Peter Maydell &lt;peter.maydell@linaro.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>target/loongarch: Add gdb support.</title>
<updated>2022-06-06T18:14:13+00:00</updated>
<author>
<name>Xiaojuan Yang</name>
</author>
<published>2022-06-06T12:43:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=ca61e75071c647cf93b3161a228c6a54178cd58c'/>
<id>urn:sha1:ca61e75071c647cf93b3161a228c6a54178cd58c</id>
<content type='text'>
Signed-off-by: Xiaojuan Yang &lt;yangxiaojuan@loongson.cn&gt;
Signed-off-by: Song Gao &lt;gaosong@loongson.cn&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-Id: &lt;20220606124333.2060567-42-yangxiaojuan@loongson.cn&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
</feed>
