Experimental fork of QEMU with video encoding patches https://git.openslx.org/bwlp/qemu.git/atom/docs/system/arm?h=master 2022-11-05T19:35:45+00:00 2022-11-05T19:35:45+00:00 Stefan Weil 2022-10-30T10:59:44+00:00 urn:sha1:1e458f11273c315ee2045f6e632b8dfb5f2b1544 Most of them were found and fixed using codespell. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20221030105944.311940-1-sw@weilnetz.de> Signed-off-by: Laurent Vivier <laurent@vivier.eu> 2022-10-27T09:27:24+00:00 Richard Henderson 2022-10-24T05:18:49+00:00 urn:sha1:71943a1e9084dde71cabba5895920f3a0c54de9b Perform the atomic update for hardware management of the access flag. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20221024051851.3074715-13-richard.henderson@linaro.org [PMM: Fix accidental PROT_WRITE to PAGE_WRITE; add missing main-loop.h include] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> 2022-10-27T09:27:23+00:00 Peter Maydell 2022-10-21T16:01:31+00:00 urn:sha1:e4c93e44ab103f6c67abd85d620343f61aafa004 FEAT_E0PD adds new bits E0PD0 and E0PD1 to TCR_EL1, which allow the OS to forbid EL0 access to half of the address space. Since this is an EL0-specific variation on the existing TCR_ELx.{EPD0,EPD1}, we can implement it entirely in aa64_va_parameters(). This requires moving the existing regime_is_user() to internals.h so that the code in helper.c can get at it. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20221021160131.3531787-1-peter.maydell@linaro.org 2022-10-10T13:52:25+00:00 Peter Maydell 2022-10-03T16:23:15+00:00 urn:sha1:915f62844cf62e428c7c178149b5ff1cbe129b07 FEAT_GTG is a change tho the ID register ID_AA64MMFR0_EL1 so that it can report a different set of supported granule (page) sizes for stage 1 and stage 2 translation tables. As of commit c20281b2a5048 we already report the granule sizes that way for '-cpu max', and now we also correctly make attempts to use unimplemented granule sizes fail, so we can report the support of the feature in the documentation. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20221003162315.2833797-4-peter.maydell@linaro.org 2022-10-10T13:52:24+00:00 Joel Stanley 2022-10-04T05:00:42+00:00 urn:sha1:86a85d73e3167c97da8f9680536af89e66943b76 openpower.xyz was retired some time ago. The OpenBMC Jenkins is where images can be found these days. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20221004050042.22681-1-joel@jms.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org> 2022-09-14T10:19:40+00:00 Peter Maydell 2022-08-22T13:23:58+00:00 urn:sha1:e31e0f56616ae88cda22da8d5a257c2fcee4de2a Update the ID registers for TCG's '-cpu max' to report a FEAT_PMUv3p5 compliant PMU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220822132358.3524971-11-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2022-09-14T10:19:40+00:00 Peter Maydell 2022-08-19T11:00:51+00:00 urn:sha1:3fe72e213eae33daaea88685878a571bd5ef3e08 The architectural feature FEAT_ETS (Enhanced Translation Synchronization) is a set of tightened guarantees about memory ordering involving translation table walks: * if memory access RW1 is ordered-before memory access RW2 then it is also ordered-before any translation table walk generated by RW2 that generates a translation fault, address size fault or access fault * TLB maintenance on non-exec-permission translations is guaranteed complete after a DSB (ie it does not need the context synchronization event that you have to have if you don’t have FEAT_ETS) For QEMU’s implementation we don’t reorder translation table walk accesses, and we guarantee to finish the TLB maintenance as soon as the TLB op is done (the tlb_flush functions will complete at the end of the TLB, and TLB ops always end the TB because they’re sysreg writes). So we’re already compliant and all we need to do is say so in the ID registers for the 'max' CPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220819110052.2942289-6-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2022-09-14T10:19:39+00:00 Hao Wu 2022-08-19T00:20:15+00:00 urn:sha1:3b16766b5ae7f61079e3ae674e140219c4cdbe85 Add cortex A35 core and enable it for virt board. Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220819002015.1663247-1-wuhaotsh@google.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2022-08-01T09:58:02+00:00 Daniel P. Berrangé 2022-07-07T16:37:15+00:00 urn:sha1:7a21bee2aa52fc95b25e38372678986ee94f05f1 Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20220707163720.1421716-5-berrange@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com> 2022-07-14T14:24:38+00:00 Cédric Le Goater 2022-07-14T14:24:38+00:00 urn:sha1:1d6fb3d05888578fdb09600fef4e9e90e652010d Some more controllers have been modeled recently. Reflect that in the list of supported devices. New machines were also added. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Peter Delevoryas <peter@pjd.dev> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-Id: <20220706172131.809255-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>