<feed xmlns='http://www.w3.org/2005/Atom'>
<title>bwlp/qemu.git/docs/system/riscv, branch spice_video_codecs</title>
<subtitle>Experimental fork of QEMU with video encoding patches</subtitle>
<id>https://git.openslx.org/bwlp/qemu.git/atom/docs/system/riscv?h=spice_video_codecs</id>
<link rel='self' href='https://git.openslx.org/bwlp/qemu.git/atom/docs/system/riscv?h=spice_video_codecs'/>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/'/>
<updated>2022-09-26T21:04:38+00:00</updated>
<entry>
<title>docs/system: clean up code escape for riscv virt platform</title>
<updated>2022-09-26T21:04:38+00:00</updated>
<author>
<name>Alex Bennée</name>
</author>
<published>2022-09-05T16:39:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=0c2d4671916333e5b66fd923279fb6fb62315bed'/>
<id>urn:sha1:0c2d4671916333e5b66fd923279fb6fb62315bed</id>
<content type='text'>
The example code is rendered slightly mangled due to missing code
block. Properly escape the code block and add shell prompt and qemu to
fit in with the other examples on the page.

Signed-off-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Reviewed-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
Message-Id: &lt;20220905163939.1599368-1-alex.bennee@linaro.org&gt;
Signed-off-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
</content>
</entry>
<entry>
<title>hw/riscv: Enable TPM backends</title>
<updated>2022-04-29T00:48:48+00:00</updated>
<author>
<name>Alistair Francis</name>
</author>
<published>2022-04-27T23:41:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=325b7c4e7582c229d28c47123c3b986ed948eb84'/>
<id>urn:sha1:325b7c4e7582c229d28c47123c3b986ed948eb84</id>
<content type='text'>
Imply the TPM sysbus devices. This allows users to add TPM devices to
the RISC-V virt board.

This was tested by first creating an emulated TPM device:

    swtpm socket --tpm2 -t -d --tpmstate dir=/tmp/tpm \
        --ctrl type=unixio,path=swtpm-sock

Then launching QEMU with:

    -chardev socket,id=chrtpm,path=swtpm-sock \
    -tpmdev emulator,id=tpm0,chardev=chrtpm \
    -device tpm-tis-device,tpmdev=tpm0

The TPM device can be seen in the memory tree and the generated device
tree.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/942
Signed-off-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
Reviewed-by: Edgar E. Iglesias &lt;edgar.iglesias@amd.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Message-Id: &lt;20220427234146.1130752-7-alistair.francis@opensource.wdc.com&gt;
Signed-off-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
</content>
</entry>
<entry>
<title>docs/system: riscv: Document AIA options for virt machine</title>
<updated>2022-03-03T03:14:50+00:00</updated>
<author>
<name>Anup Patel</name>
</author>
<published>2022-02-20T08:55:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=c65bc383edc7aa7c12afcdad3be30521b3280203'/>
<id>urn:sha1:c65bc383edc7aa7c12afcdad3be30521b3280203</id>
<content type='text'>
We have two new machine options "aia" and "aia-guests" available
for the RISC-V virt machine so let's document these options.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
Reviewed-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
Reviewed-by: Frank Chang &lt;frank.chang@sifive.com&gt;
Message-Id: &lt;20220220085526.808674-5-anup@brainfault.org&gt;
Signed-off-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
</content>
</entry>
<entry>
<title>docs/system: riscv: Update description of CPU</title>
<updated>2022-02-16T02:25:52+00:00</updated>
<author>
<name>Yu Li</name>
</author>
<published>2022-02-08T13:07:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=7035b8420fa52e8c94cf4317c0f88c1b73ced28d'/>
<id>urn:sha1:7035b8420fa52e8c94cf4317c0f88c1b73ced28d</id>
<content type='text'>
Since the hypervisor extension been non experimental and enabled for
default CPU, the previous command is no longer available and the
option `x-h=true` or `h=true` is also no longer required.

Signed-off-by: Yu Li &lt;liyu.yukiteru@bytedance.com&gt;
Reviewed-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
Message-Id: &lt;9040401e-8f87-ef4a-d840-6703f08d068c@bytedance.com&gt;
Signed-off-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
</content>
</entry>
<entry>
<title>Fix some typos in documentation (found by codespell)</title>
<updated>2021-11-22T14:02:38+00:00</updated>
<author>
<name>Stefan Weil</name>
</author>
<published>2021-11-17T21:07:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=b980c1aec63908074040e5cab135728e3b5db117'/>
<id>urn:sha1:b980c1aec63908074040e5cab135728e3b5db117</id>
<content type='text'>
Signed-off-by: Stefan Weil &lt;sw@weilnetz.de&gt;
Message-Id: &lt;20211117210702.1393570-1-sw@weilnetz.de&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;philmd@redhat.com&gt;
[thuth: "what's" --&gt; "what is" as suggested by philmd]
Signed-off-by: Thomas Huth &lt;thuth@redhat.com&gt;
</content>
</entry>
<entry>
<title>docs/system/riscv: sifive_u: Update U-Boot instructions</title>
<updated>2021-09-20T21:56:49+00:00</updated>
<author>
<name>Bin Meng</name>
</author>
<published>2021-09-11T15:34:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=758c07c9fca1ad9716820feb346cec0553968011'/>
<id>urn:sha1:758c07c9fca1ad9716820feb346cec0553968011</id>
<content type='text'>
In U-Boot v2021.07 release, there were 2 major changes for the
SiFive Unleashed board support:

- Board config name was changed from sifive_fu540_defconfig to
  sifive_unleashed_defconfig
- The generic binman tool was used to generate the FIT image
  (combination of U-Boot proper, DTB and OpenSBI firmware)

which make the existing U-Boot instructions out of date.

Update the doc with latest instructions.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
Message-id: 20210911153431.10362-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
</content>
</entry>
<entry>
<title>hw/riscv: virt: Add optional ACLINT support to virt machine</title>
<updated>2021-09-20T21:56:49+00:00</updated>
<author>
<name>Anup Patel</name>
</author>
<published>2021-08-31T11:06:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=954886ea6dd496ad259f8c576a8767e1d7059a28'/>
<id>urn:sha1:954886ea6dd496ad259f8c576a8767e1d7059a28</id>
<content type='text'>
We extend virt machine to emulate ACLINT devices only when "aclint=on"
parameter is passed along with machine name in QEMU command-line.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Message-id: 20210831110603.338681-5-anup.patel@wdc.com
Signed-off-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
</content>
</entry>
<entry>
<title>sifive_u: Connect the SiFive PWM device</title>
<updated>2021-09-20T21:56:49+00:00</updated>
<author>
<name>Alistair Francis</name>
</author>
<published>2021-09-09T03:55:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=ea6eaa0604d2ad66636f968842fe9ff315b065c8'/>
<id>urn:sha1:ea6eaa0604d2ad66636f968842fe9ff315b065c8</id>
<content type='text'>
Connect the SiFive PWM device and expose it via the device tree.

Signed-off-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Message-id: 22f98648b4e012f78529a56f5ca60b0b27852a4d.1631159656.git.alistair.francis@wdc.com
</content>
</entry>
<entry>
<title>docs: Format literals correctly</title>
<updated>2021-08-02T10:42:38+00:00</updated>
<author>
<name>Peter Maydell</name>
</author>
<published>2021-07-26T14:23:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=6df743dc31a6a0b618042da2b550993c6e9767d1'/>
<id>urn:sha1:6df743dc31a6a0b618042da2b550993c6e9767d1</id>
<content type='text'>
In rST markup, single backticks `like this` represent "interpreted
text", which can be handled as a bunch of different things if tagged
with a specific "role":
https://docutils.sourceforge.io/docs/ref/rst/restructuredtext.html#interpreted-text
(the most common one for us is "reference to a URL, which gets
hyperlinked").

The default "role" if none is specified is "title_reference",
intended for references to book or article titles, and it renders
into the HTML as &lt;cite&gt;...&lt;/cite&gt; (usually comes out as italics).

This commit fixes various places in the manual which were
using single backticks when double backticks (for literal text)
were intended, and covers those files where only one or two
instances of these errors were made.

Signed-off-by: Peter Maydell &lt;peter.maydell@linaro.org&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot</title>
<updated>2021-07-14T22:56:00+00:00</updated>
<author>
<name>Bin Meng</name>
</author>
<published>2021-07-06T09:50:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=6165dcb55f0ab4b2a241e49859ce6262157887e7'/>
<id>urn:sha1:6165dcb55f0ab4b2a241e49859ce6262157887e7</id>
<content type='text'>
This adds a new section in the documentation to demonstrate how to
use the new direct kernel boot feature for Microchip Icicle Kit,
other than the HSS bootflow, using an upstream U-Boot v2021.07 image
as an example.

It also updates the truth table to have a new '-dtb' column which is
required by direct kernel boot.

Signed-off-by: Bin Meng &lt;bin.meng@windriver.com&gt;
Reviewed-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
Message-id: 20210706095045.1917913-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
</content>
</entry>
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