Experimental fork of QEMU with video encoding patches https://git.openslx.org/bwlp/qemu.git/atom/hw/misc/Kconfig?h=spice_video_codecs 2022-05-08T17:52:37+00:00 2022-05-08T17:52:37+00:00 Mark Cave-Ayland 2022-05-04T09:25:52+00:00 urn:sha1:45f569a11666051f98edc678616d135c9feaf506 Move the LASI device implementation from hw/hppa to hw/misc so that it is located with all the other miscellaneous devices. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Helge Deller <deller@gmx.de> Message-Id: <20220504092600.10048-43-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> 2021-06-17T12:10:32+00:00 Corey Minyard 2021-05-18T21:08:03+00:00 urn:sha1:5e9ae4b1a31a17a72487372067a78b6afa68b68d Lots of this are expected to be coming in, create a directory for them. Also move the tmp105.h file into the include directory where it should be. Cc: Cédric Le Goater <clg@kaod.org> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Andrew Jeffery <andrew@aj.id.au> Cc: Joel Stanley <joel@jms.id.au> Cc: Andrzej Zaborowski <balrogg@gmail.com> Cc: qemu-arm@nongnu.org Signed-off-by: Corey Minyard <cminyard@mvista.com> Acked-by: Cédric Le Goater <clg@kaod.org> 2021-06-17T12:10:32+00:00 Corey Minyard 2021-05-18T20:54:52+00:00 urn:sha1:58f3e3fe69a66a5c27675faf3e7afa52e027e621 It's an adc, put it where it belongs. Cc: Andrzej Zaborowski <balrogg@gmail.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: qemu-arm@nongnu.org Signed-off-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> 2021-03-15T20:02:57+00:00 Laurent Vivier 2021-03-12T21:41:44+00:00 urn:sha1:0791bc02b8fbf9d55626b57f45255ba1b6ea83d5 Add a system controller for the m68k-virt machine. This controller allows the kernel to power off or reset the machine. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210312214145.2936082-5-laurent@vivier.eu> 2021-03-08T17:20:02+00:00 Peter Maydell 2021-02-19T14:45:53+00:00 urn:sha1:4239b311467bea86578d9da3cd22909de69d7af7 The SSE-300 has a new register block CPU<N>_PWRCTRL. There is one instance of this per CPU in the system (so just one for the SSE-300), and as well as the usual CIDR/PIDR ID registers it has just one register, CPUPWRCFG. This register allows the guest to configure behaviour of the system in power-down and deep-sleep states. Since QEMU does not model those, we make the register a dummy reads-as-written implementation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-21-peter.maydell@linaro.org 2021-03-08T17:20:02+00:00 Peter Maydell 2021-02-19T14:45:52+00:00 urn:sha1:370d75d935c4f58a3f94597a9e6609aefbc5bb34 The ARMSSE_CPUID and ARMSSE_MHU Kconfig stanzas are for the devices implemented by hw/misc/cpuid.c and hw/misc/armsse-mhu.c. Move them to hw/misc/Kconfig where they belong. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-20-peter.maydell@linaro.org 2021-01-29T10:47:28+00:00 Mihai Carabas 2021-01-27T14:59:28+00:00 urn:sha1:d097b3dcb6214a35613abc60c48517b850349ad0 Add PCI interface support for PVPANIC device. Create a new file pvpanic-pci.c where the PCI specific routines reside and update the build system with the new files and config structure. Signed-off-by: Mihai Carabas <mihai.carabas@oracle.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Mihai Carabas <mihai.carabas@oracle.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> 2021-01-29T10:47:28+00:00 Mihai Carabas 2021-01-27T14:59:27+00:00 urn:sha1:677726ef1ebc567e4f5081f68623debc68f958d9 To ease the PCI device addition in next patches, split the code as follows: - generic code (read/write/setup) is being kept in pvpanic.c - ISA dependent code moved to pvpanic-isa.c Also, rename: - ISA_PVPANIC_DEVICE -> PVPANIC_ISA_DEVICE. - TYPE_PVPANIC -> TYPE_PVPANIC_ISA. - MemoryRegion io -> mr. - pvpanic_ioport_* in pvpanic_*. Update the build system with the new files and config structure. Signed-off-by: Mihai Carabas <mihai.carabas@oracle.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> 2020-12-10T11:11:03+00:00 John Wang 2020-12-10T11:11:03+00:00 urn:sha1:5e623f2bf1b4a43022c2fd31919c76ddb9556e17 Largely inspired by the TMP421 temperature sensor, here is a model for the EMC1413/EMC1414 temperature sensors. Specs can be found here : http://ww1.microchip.com/downloads/en/DeviceDoc/20005274A.pdf Signed-off-by: John Wang <wangzhiqiang.bj@bytedance.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20201122105134.671-1-wangzhiqiang.bj@bytedance.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> 2020-11-03T15:17:23+00:00 Bin Meng 2020-10-28T05:30:06+00:00 urn:sha1:0f25065cb616f74729383fbf30369c374305ebb1 This creates a minimum model for Microchip PolarFire SoC SYSREG module. It only implements the ENVM_CR register to tell guest software that eNVM is running at the configured divider rate. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1603863010-15807-7-git-send-email-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>