bwlp/qemu.git/hw/openrisc, branch spice_video_codecs

openrisc: re-randomize rng-seed on reboot

2022-10-27T10:34:31+00:00

When the system reboots, the rng-seed that the FDT has should be re-randomized, so that the new boot gets a new seed. Since the FDT is in the ROM region at this point, we add a hook right after the ROM has been added, so that we have a pointer to that copy of the FDT. Cc: Stafford Horne Signed-off-by: Jason A. Donenfeld Message-id: 20221025004327.568476-11-Jason@zx2c4.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell

hw/openrisc: virt: pass random seed to fdt

2022-09-04T06:02:57+00:00

If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to initialize early. Set this using the usual guest random number generation function. This is confirmed to successfully initialize the RNG on Linux 5.19-rc2. Signed-off-by: Jason A. Donenfeld Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne

hw/openrisc: Initialize timer time at startup

2022-09-04T06:02:57+00:00

The last_clk time was initialized at zero, this means when we calculate the first delta we will calculate 0 vs current time which could cause unnecessary hops. This patch moves timer initialization to the cpu reset. There are two resets registered here: 1. Per cpu timer mask (ttmr) reset. 2. Global cpu timer (last_clk and ttcr) reset, attached to the first cpu only. Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne

hw/openrisc: Add PCI bus support to virt

2022-09-04T06:02:57+00:00

This is mostly borrowed from xtensa and riscv as examples. The create_pcie_irq_map swizzle function is almost and exact copy but here we use a single cell interrupt, possibly we can make this generic. Signed-off-by: Stafford Horne

hw/openrisc: Add the OpenRISC virtual machine

2022-09-04T06:02:57+00:00

This patch adds the OpenRISC virtual machine 'virt' for OpenRISC. This platform allows for a convenient CI platform for toolchain, software ports and the OpenRISC linux kernel port. Much of this has been sourced from the m68k and riscv virt platforms. The platform provides: - OpenRISC SMP with up to 4 cpus - A virtio bus with up to 8 devices - Standard ns16550a serial - Goldfish RTC - SiFive TEST device for poweroff and reboot - Generated Device Tree to automatically configure the guest kernel Signed-off-by: Stafford Horne

hw/openrisc: Split re-usable boot time apis out to boot.c

2022-09-04T06:02:56+00:00

These will be shared with the virt platform. Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne

hw/openrisc: use right OMPIC size variable

2022-05-15T01:33:01+00:00

This appears to be a copy and paste error. The UART size was used instead of the much smaller OMPIC size. But actually that smaller OMPIC size is wrong too and doesn't allow the IPI to work in Linux. So set it to the old value. Signed-off-by: Jason A. Donenfeld [smh:Updated OR1KSIM_OMPIC size to use OR1KSIM_CPUS_MAX] Signed-off-by: Stafford Horne

hw/openrisc: support 4 serial ports in or1ksim

2022-05-15T01:31:46+00:00

The 8250 serial controller supports 4 serial ports, so wire them all up, so that we can have more than one basic I/O channel. Cc: Stafford Horne Signed-off-by: Jason A. Donenfeld [smh:Fixup indentation and lines over 80 chars] Signed-off-by: Stafford Horne

hw/openrisc: page-align FDT address

2022-05-03T20:23:37+00:00

The QEMU-provided FDT was only being recognized by the kernel when it was used in conjunction with -initrd. Without it, the magic bytes wouldn't be there and the kernel couldn't load it. This patch fixes the issue by page aligning the provided FDT. Cc: Stafford Horne Cc: Peter Maydell Signed-off-by: Jason A. Donenfeld Signed-off-by: Stafford Horne

hw/openrisc/openrisc_sim: Add support for initrd loading

2022-02-26T01:39:36+00:00

The initrd passed via the command line is loaded into memory. It's location and size is then added to the device tree so the kernel knows where to find it. Signed-off-by: Stafford Horne Reviewed-by: Peter Maydell