bwlp/qemu.git/hw/ppc/pnv_xscom.c, branch spice_video_codecs

ppc/pnv: Add initial P9/10 SBE model

2022-08-31T17:08:05+00:00

The SBE (Self Boot Engine) are on-chip microcontrollers that perform early boot steps, as well as provide some runtime facilities (e.g., timer, secure register access, MPIPL). The latter facilities are accessed mostly via a message system called SBEFIFO. This driver provides initial emulation for the SBE runtime registers and a very basic SBEFIFO implementation that provides the timer command. This covers the basic SBE behaviour expected by skiboot when booting. Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin Message-Id: <20220811093726.1442343-1-npiggin@gmail.com> [danielhb: fixed SBE_HOST_RESPONSE_MASK long line] Signed-off-by: Daniel Henrique Barboza

ppc/pnv: Add a comment on the "primary-topology-index" property

2021-09-29T09:37:38+00:00

On P10, the chip id is calculated from the "Primary topology table index". See skiboot commits for more information [1]. This information is extracted from the hdata on real systems which QEMU needs to emulate. Add this property for all machines even if it is only used on POWER10. [1] https://github.com/open-power/skiboot/commit/2ce3f083f399 https://github.com/open-power/skiboot/commit/a2d4d7f9e14a Signed-off-by: Cédric Le Goater Message-Id: <20210901094153.227671-4-clg@kaod.org> Signed-off-by: David Gibson

ppc/pnv: add a chip topology index for POWER10

2021-08-27T02:41:13+00:00

Signed-off-by: Cédric Le Goater Message-Id: <20210809134547.689560-7-clg@kaod.org> Signed-off-by: David Gibson

exec/memory: Use struct Object typedef

2021-03-09T20:53:57+00:00

We forward-declare Object typedef in "qemu/typedefs.h" since commit ca27b5eb7cd ("qom/object: Move Object typedef to 'qemu/typedefs.h'"). Use it everywhere to make the code simpler. Signed-off-by: Philippe Mathieu-Daudé Acked-by: David Gibson Reviewed-by: Laurent Vivier Message-Id: <20210225182003.3629342-1-philmd@redhat.com> Signed-off-by: Laurent Vivier

non-virt: Fix Lesser GPL version number

2020-11-15T15:38:24+00:00

There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Signed-off-by: Chetan Pant Message-Id: <20201016145346.27167-1-chetan4windows@gmail.com> Reviewed-by: Thomas Huth Reviewed-by: Cédric Le Goater Signed-off-by: Thomas Huth

ppc/pnv: Introduce PnvChipClass::xscom_pcba() method

2019-12-16T23:59:11+00:00

The XSCOM bus is implemented with a QOM interface, which is mostly generic from a CPU type standpoint, except for the computation of addresses on the Pervasive Connect Bus (PCB) network. This is handled by the pnv_xscom_pcba() function with a switch statement based on the chip_type class level attribute of the CPU chip. This can be achieved using QOM. Also the address argument is masked with PNV_XSCOM_SIZE - 1, which is for POWER8 only. Addresses may have different sizes with other CPU types. Have each CPU chip type handle the appropriate computation with a QOM xscom_pcba() method. Signed-off-by: Greg Kurz Message-Id: <157623843543.360005.13996472463887521794.stgit@bahia.lan> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson

ppc/pnv: Pass content of the "compatible" property to pnv_dt_xscom()

2019-12-16T23:59:11+00:00

Since pnv_dt_xscom() is called from chip specific dt_populate() hooks, it shouldn't have to guess the chip type in order to populate the "compatible" property. Just pass the compat string and its size as arguments. Signed-off-by: Greg Kurz Message-Id: <157623842430.360005.9513965612524265862.stgit@bahia.lan> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson

ppc/pnv: Pass XSCOM base address and address size to pnv_dt_xscom()

2019-12-16T23:59:11+00:00

Since pnv_dt_xscom() is called from chip specific dt_populate() hooks, it shouldn't have to guess the chip type in order to populate the "reg" property. Just pass the base address and address size as arguments. Signed-off-by: Greg Kurz Message-Id: <157623841868.360005.17577624823547136435.stgit@bahia.lan> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson

ppc/pnv: Introduce PBA registers

2019-12-16T23:39:48+00:00

The PBA bridge unit (Power Bus Access) connects the OCC (On Chip Controller) to the Power bus and System Memory. The PBA is used to gather sensor data, for power management, for sleep states, for initial boot, among other things. The PBA logic provides a set of four registers PowerBus Access Base Address Registers (PBABAR0..3) which map the OCC address space to the PowerBus space. These registers are setup by the initial FW and define the PowerBus Range of system memory that can be accessed by PBA. The current modeling of the PBABAR registers is done under the common XSCOM handlers. We introduce a specific XSCOM regions for these registers and fix : - BAR sizes and BAR masks - The mapping of the OCC common area. It is common to all chips and should be mapped once. We will address per-OCC area in the next change. - OCC common area is in BAR 3 on P8 Inspired by previous work of Balamuruhan S Signed-off-by: Cédric Le Goater Message-Id: <20191211082912.2625-2-clg@kaod.org> Signed-off-by: David Gibson

ppc/pnv: populate the DT with realized XSCOM devices

2019-12-16T23:39:48+00:00

Some devices could be initialized in the instance_init handler but not realized for configuration reasons. Nodes should not be added in the DT for such devices. Signed-off-by: Cédric Le Goater Message-Id: <20191210135845.19773-3-clg@kaod.org> Reviewed-by: Greg Kurz Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: David Gibson