<feed xmlns='http://www.w3.org/2005/Atom'>
<title>bwlp/qemu.git/hw/ppc/ppc440.h, branch spice_video_codecs</title>
<subtitle>Experimental fork of QEMU with video encoding patches</subtitle>
<id>https://git.openslx.org/bwlp/qemu.git/atom/hw/ppc/ppc440.h?h=spice_video_codecs</id>
<link rel='self' href='https://git.openslx.org/bwlp/qemu.git/atom/hw/ppc/ppc440.h?h=spice_video_codecs'/>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/'/>
<updated>2022-10-17T19:15:09+00:00</updated>
<entry>
<title>ppc440_sdram: QOM'ify</title>
<updated>2022-10-17T19:15:09+00:00</updated>
<author>
<name>BALATON Zoltan</name>
</author>
<published>2022-09-24T12:28:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=5f7effe4df91702add08e3e3dc1871fd35a8903f'/>
<id>urn:sha1:5f7effe4df91702add08e3e3dc1871fd35a8903f</id>
<content type='text'>
Change the ppc440_sdram model to a QOM class derived from the
PPC4xx-dcr-device and name it ppc4xx-sdram-ddr2. This is mostly
modelling the DDR2 SDRAM controller found in the 460EX (used on the
sam460ex board). Newer SoCs (regardless of their PPC core, e.g. 405EX)
may have this controller but we only emulate enough of it for the
sam460ex u-boot firmware.

Signed-off-by: BALATON Zoltan &lt;balaton@eik.bme.hu&gt;
Reviewed-by: Cédric Le Goater &lt;clg@kaod.org&gt;
Message-Id: &lt;3e82ae575c7c41e464a0082d55ecb4ebcc4d4329.1664021647.git.balaton@eik.bme.hu&gt;
Signed-off-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
</content>
</entry>
<entry>
<title>ppc440_sdram: Move RAM size check to ppc440_sdram_init</title>
<updated>2022-10-17T19:15:09+00:00</updated>
<author>
<name>BALATON Zoltan</name>
</author>
<published>2022-09-24T12:28:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=ef10aebb9a71f0c60f0b7aae808498333bb7bfd9'/>
<id>urn:sha1:ef10aebb9a71f0c60f0b7aae808498333bb7bfd9</id>
<content type='text'>
Move the check for valid memory sizes from board to sdram controller
init. This adds the missing valid memory sizes of 16 and 8 MiB to the
DoC and the board now only checks for additional restrictions imposed
by its firmware then sdram init checks for valid sizes for SoC.

Signed-off-by: BALATON Zoltan &lt;balaton@eik.bme.hu&gt;
Reviewed-by: Cédric Le Goater &lt;clg@kaod.org&gt;
Message-Id: &lt;41da3797392acaacc7963b79512c8af8005fa4b0.1664021647.git.balaton@eik.bme.hu&gt;
[danielhb: avoid 4*GiB size due to 32 bit build problems]
Signed-off-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
</content>
</entry>
<entry>
<title>ppc440_sdram: Get rid of the init RAM hack</title>
<updated>2022-10-17T19:15:09+00:00</updated>
<author>
<name>BALATON Zoltan</name>
</author>
<published>2022-09-24T12:28:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=03f7041bfdc45f6c981a83fd2d932bad161769ad'/>
<id>urn:sha1:03f7041bfdc45f6c981a83fd2d932bad161769ad</id>
<content type='text'>
Remove the do_init parameter of ppc440_sdram_init and enable SDRAM
controller from the board. Firmware does this so it may only be needed
when booting with -kernel without firmware but we enable SDRAM
unconditionally to preserve previous behaviour.

Signed-off-by: BALATON Zoltan &lt;balaton@eik.bme.hu&gt;
Reviewed-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
Message-Id: &lt;c2eda8f83c82f655aa7821a5a8c9310484bd6a1d.1664021647.git.balaton@eik.bme.hu&gt;
Signed-off-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
</content>
</entry>
<entry>
<title>ppc4xx: Use Ppc4xxSdramBank in ppc4xx_sdram_banks()</title>
<updated>2022-10-17T19:15:09+00:00</updated>
<author>
<name>BALATON Zoltan</name>
</author>
<published>2022-09-24T12:27:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=734c44ea13272c3b3d5cd9345cc4df7ce9bd30b3'/>
<id>urn:sha1:734c44ea13272c3b3d5cd9345cc4df7ce9bd30b3</id>
<content type='text'>
Change ppc4xx_sdram_banks() to take one Ppc4xxSdramBank array instead
of the separate arrays and adjust ppc4xx_sdram_init() and
ppc440_sdram_init() accordingly as well as machines using these.

Signed-off-by: BALATON Zoltan &lt;balaton@eik.bme.hu&gt;
Reviewed-by: Cédric Le Goater &lt;clg@kaod.org&gt;
Message-Id: &lt;e3a1fea51f29779fd6a61be90a29c684f3299544.1664021647.git.balaton@eik.bme.hu&gt;
Signed-off-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
</content>
</entry>
<entry>
<title>ppc440_uc: Basic emulation of PPC440 DMA controller</title>
<updated>2018-07-02T23:56:52+00:00</updated>
<author>
<name>BALATON Zoltan</name>
</author>
<published>2018-06-29T12:04:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=3c409c1927efde2fc7ac5f6cd5d79d0784be3b5d'/>
<id>urn:sha1:3c409c1927efde2fc7ac5f6cd5d79d0784be3b5d</id>
<content type='text'>
PPC440 SoCs such as the AMCC 460EX have a DMA controller which is used
by AmigaOS on the sam460ex. Implement the parts used by AmigaOS so it
can get further booting on the sam460ex machine.

Signed-off-by: BALATON Zoltan &lt;balaton@eik.bme.hu&gt;
Signed-off-by: David Gibson &lt;david@gibson.dropbear.id.au&gt;
</content>
</entry>
<entry>
<title>ppc4xx: Add device models found in PPC440 core SoCs</title>
<updated>2018-02-16T03:06:07+00:00</updated>
<author>
<name>BALATON Zoltan</name>
</author>
<published>2018-02-15T21:27:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=58d5b22bbd505dc942d137d5d3da89ad9bc16c0a'/>
<id>urn:sha1:58d5b22bbd505dc942d137d5d3da89ad9bc16c0a</id>
<content type='text'>
These devices are found in newer SoCs based on 440 core e.g. the 460EX
(http://www.embeddeddeveloper.com/assets/processors/amcc/datasheets/
PP460EX_DS2063.pdf)

Signed-off-by: BALATON Zoltan &lt;balaton@eik.bme.hu&gt;
Signed-off-by: David Gibson &lt;david@gibson.dropbear.id.au&gt;
</content>
</entry>
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