<feed xmlns='http://www.w3.org/2005/Atom'>
<title>bwlp/qemu.git/hw/ppc/trace-events, branch spice_video_codecs</title>
<subtitle>Experimental fork of QEMU with video encoding patches</subtitle>
<id>https://git.openslx.org/bwlp/qemu.git/atom/hw/ppc/trace-events?h=spice_video_codecs</id>
<link rel='self' href='https://git.openslx.org/bwlp/qemu.git/atom/hw/ppc/trace-events?h=spice_video_codecs'/>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/'/>
<updated>2022-10-28T16:15:23+00:00</updated>
<entry>
<title>ppc4xx_sdram: Generalise bank setup</title>
<updated>2022-10-28T16:15:23+00:00</updated>
<author>
<name>BALATON Zoltan</name>
</author>
<published>2022-10-19T16:02:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=424a660c58a6b950363d42b79a30e651c1037550'/>
<id>urn:sha1:424a660c58a6b950363d42b79a30e651c1037550</id>
<content type='text'>
Currently only base and size are set on initial bank creation and bcr
value is computed on mapping the region. Set bcr at init so the bcr
encoding method becomes local to the controller model and mapping and
unmapping can operate on the bank so it can be shared between
different controller models. This patch converts the DDR2 controller.

Signed-off-by: BALATON Zoltan &lt;balaton@eik.bme.hu&gt;
Message-Id: &lt;51b957b4b2d714a1072aa2589b979e08411640df.1666194485.git.balaton@eik.bme.hu&gt;
Signed-off-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
</content>
</entry>
<entry>
<title>target/ppc: define PPC_INTERRUPT_* values directly</title>
<updated>2022-10-28T16:15:22+00:00</updated>
<author>
<name>Matheus Ferst</name>
</author>
<published>2022-10-11T20:48:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=f003109f710bb39a78c27ce18aa10579340f5a3f'/>
<id>urn:sha1:f003109f710bb39a78c27ce18aa10579340f5a3f</id>
<content type='text'>
This enum defines the bit positions in env-&gt;pending_interrupts for each
interrupt. However, except for the comparison in kvmppc_set_interrupt,
the values are always used as (1 &lt;&lt; PPC_INTERRUPT_*). Define them
directly like that to save some clutter. No functional change intended.

Reviewed-by: David Gibson &lt;david@gibson.dropbear.id.au&gt;
Signed-off-by: Matheus Ferst &lt;matheus.ferst@eldorado.org.br&gt;
Message-Id: &lt;20221011204829.1641124-2-matheus.ferst@eldorado.org.br&gt;
Signed-off-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
</content>
</entry>
<entry>
<title>ppc/ppc405: QOM'ify OPBA</title>
<updated>2022-08-31T17:08:06+00:00</updated>
<author>
<name>Cédric Le Goater</name>
</author>
<published>2022-08-17T15:08:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=72beecc20c72fefb97bc4a4e558ba4e884166629'/>
<id>urn:sha1:72beecc20c72fefb97bc4a4e558ba4e884166629</id>
<content type='text'>
The OPB arbitrer is currently modeled as a simple SysBus device with a
unique memory region.

Reviewed-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
Signed-off-by: Cédric Le Goater &lt;clg@kaod.org&gt;
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan &lt;balaton@eik.bme.hu&gt;
Message-Id: &lt;38476bc43d2332db2f09dbede9eff5234d6ce217.1660746880.git.balaton@eik.bme.hu&gt;
Signed-off-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
</content>
</entry>
<entry>
<title>ppc/ppc405: QOM'ify GPIO</title>
<updated>2022-08-31T17:08:06+00:00</updated>
<author>
<name>Cédric Le Goater</name>
</author>
<published>2022-08-17T15:08:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=125277c6a88d93760c2ec28c74bf3a1c30b90113'/>
<id>urn:sha1:125277c6a88d93760c2ec28c74bf3a1c30b90113</id>
<content type='text'>
The GPIO controller is currently modeled as a simple SysBus device
with a unique memory region.

Reviewed-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
Signed-off-by: Cédric Le Goater &lt;clg@kaod.org&gt;
[balaton: Simplify sysbus device casts for readability]
Signed-off-by: BALATON Zoltan &lt;balaton@eik.bme.hu&gt;
Message-Id: &lt;e95d7849f3768e1f9a2846c4b282392750678b3e.1660746880.git.balaton@eik.bme.hu&gt;
Signed-off-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
</content>
</entry>
<entry>
<title>ppc/ppc405: QOM'ify GPT</title>
<updated>2022-08-31T17:08:06+00:00</updated>
<author>
<name>Cédric Le Goater</name>
</author>
<published>2022-08-17T15:08:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=269fbb5b8ac0506b872ad3df277f23de1856ed15'/>
<id>urn:sha1:269fbb5b8ac0506b872ad3df277f23de1856ed15</id>
<content type='text'>
The GPT controller is currently modeled as a SysBus device with a
unique memory region, a couple of IRQs and a timer.

Reviewed-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
Signed-off-by: Cédric Le Goater &lt;clg@kaod.org&gt;
[balaton: ppc4xx_dcr_register changes, add finalize method]
Signed-off-by: BALATON Zoltan &lt;balaton@eik.bme.hu&gt;
Message-Id: &lt;8950ab26e78173f94ba65bc61bcfd0631de1fe61.1660746880.git.balaton@eik.bme.hu&gt;
[danielhb: check if timer != NULL in ppc405_gpt_finalize()]
Signed-off-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
</content>
</entry>
<entry>
<title>ppc/pnv: Add initial P9/10 SBE model</title>
<updated>2022-08-31T17:08:05+00:00</updated>
<author>
<name>Nicholas Piggin</name>
</author>
<published>2022-08-11T09:37:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=0bf4d77e5922128506a3495d72ee9f432726c085'/>
<id>urn:sha1:0bf4d77e5922128506a3495d72ee9f432726c085</id>
<content type='text'>
The SBE (Self Boot Engine) are on-chip microcontrollers that perform
early boot steps, as well as provide some runtime facilities (e.g.,
timer, secure register access, MPIPL). The latter facilities are
accessed mostly via a message system called SBEFIFO.

This driver provides initial emulation for the SBE runtime registers
and a very basic SBEFIFO implementation that provides the timer
command. This covers the basic SBE behaviour expected by skiboot when
booting.

Reviewed-by: Cédric Le Goater &lt;clg@kaod.org&gt;
Signed-off-by: Nicholas Piggin &lt;npiggin@gmail.com&gt;
Message-Id: &lt;20220811093726.1442343-1-npiggin@gmail.com&gt;
[danielhb: fixed SBE_HOST_RESPONSE_MASK long line]
Signed-off-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
</content>
</entry>
<entry>
<title>ppc/ppc405: Restore TCR and STR write handlers</title>
<updated>2022-01-04T06:55:34+00:00</updated>
<author>
<name>Cédric Le Goater</name>
</author>
<published>2022-01-04T06:55:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=cbd8f17d16c890e6d9316627e2d4def6f965988d'/>
<id>urn:sha1:cbd8f17d16c890e6d9316627e2d4def6f965988d</id>
<content type='text'>
The 405 timers were broken when booke support was added. Assumption
was made that the register numbers were the same but it's not :

    SPR_BOOKE_TSR         (0x150)
    SPR_BOOKE_TCR         (0x154)
    SPR_40x_TSR           (0x3D8)
    SPR_40x_TCR           (0x3DA)

Cc: Christophe Leroy &lt;christophe.leroy@c-s.fr&gt;
Fixes: ddd1055b07fd ("PPC: booke timers")
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Signed-off-by: Cédric Le Goater &lt;clg@kaod.org&gt;
Message-Id: &lt;20211222064025.1541490-5-clg@kaod.org&gt;
Signed-off-by: Cédric Le Goater &lt;clg@kaod.org&gt;
Message-Id: &lt;20220103063441.3424853-6-clg@kaod.org&gt;
Signed-off-by: Cédric Le Goater &lt;clg@kaod.org&gt;
</content>
</entry>
<entry>
<title>ppc/ppc4xx: Convert printfs()</title>
<updated>2022-01-04T06:55:34+00:00</updated>
<author>
<name>Cédric Le Goater</name>
</author>
<published>2022-01-04T06:55:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=b3b5c5d38f42f74e8338d864e60f2f0754978131'/>
<id>urn:sha1:b3b5c5d38f42f74e8338d864e60f2f0754978131</id>
<content type='text'>
Use a QEMU log primitive for errors and trace events for debug.

Signed-off-by: Cédric Le Goater &lt;clg@kaod.org&gt;
Reviewed-by: David Gibson &lt;david@gibson.drobear.id.au&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-Id: &lt;20211222064025.1541490-3-clg@kaod.org&gt;
Signed-off-by: Cédric Le Goater &lt;clg@kaod.org&gt;
Message-Id: &lt;20220103063441.3424853-4-clg@kaod.org&gt;
Signed-off-by: Cédric Le Goater &lt;clg@kaod.org&gt;
</content>
</entry>
<entry>
<title>ppc/ppc405: Convert printfs to trace-events</title>
<updated>2021-12-17T16:57:17+00:00</updated>
<author>
<name>Cédric Le Goater</name>
</author>
<published>2021-12-17T16:57:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=09960a5be3ec4b8caddb894ad5b73d4533ead5fb'/>
<id>urn:sha1:09960a5be3ec4b8caddb894ad5b73d4533ead5fb</id>
<content type='text'>
and one error message to a LOG_GUEST_ERROR.

Signed-off-by: Cédric Le Goater &lt;clg@kaod.org&gt;
Message-Id: &lt;20211206103712.1866296-5-clg@kaod.org&gt;
Signed-off-by: Cédric Le Goater &lt;clg@kaod.org&gt;
</content>
</entry>
<entry>
<title>ppc: Add trace-events for DCR accesses</title>
<updated>2021-12-17T16:57:17+00:00</updated>
<author>
<name>Cédric Le Goater</name>
</author>
<published>2021-12-17T16:57:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=de82dabeadd0511a3b18c76dc3c666a63798f8ae'/>
<id>urn:sha1:de82dabeadd0511a3b18c76dc3c666a63798f8ae</id>
<content type='text'>
Signed-off-by: Cédric Le Goater &lt;clg@kaod.org&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Message-Id: &lt;20211206103712.1866296-4-clg@kaod.org&gt;
Signed-off-by: Cédric Le Goater &lt;clg@kaod.org&gt;
</content>
</entry>
</feed>
