bwlp/qemu.git/hw/riscv/Makefile.objs, branch spice_video_codecs

meson: convert hw/arch*

2020-08-21T10:30:33+00:00

Each architecture's sourceset is placed in an hw_arch dictionary, and picked up from there when building the per-emulator static_library. Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini

riscv: Initial commit of OpenTitan machine

2020-06-03T16:11:51+00:00

This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng

riscv: sifive: Implement a model for SiFive FU540 OTP

2019-09-17T15:42:49+00:00

This implements a simple model for SiFive FU540 OTP (One-Time Programmable) Memory interface, primarily for reading out the stored serial number from the first 1 KiB of the 16 KiB OTP memory reserved by SiFive for internal use. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt

riscv: sifive: Implement PRCI model for FU540

2019-09-17T15:42:47+00:00

This adds a simple PRCI model for FU540 (sifive_u). It has different register layout from the existing PRCI model for FE310 (sifive_e). Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt

riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}

2019-09-17T15:42:46+00:00

Current SiFive PRCI model only works with sifive_e machine, as it only emulates registers or PRCI block in the FE310 SoC. Rename the file name to make it clear that it is for sifive_e. This also prefix "sifive_e"/"SIFIVE_E" for all macros, variables and functions. Signed-off-by: Bin Meng Reviewed-by: Chih-Min Chao Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt

hw/riscv: Split out the boot functions

2019-06-27T09:47:06+00:00

Split the common RISC-V boot functions into a seperate file. This allows us to share the common code. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Signed-off-by: Palmer Dabbelt

SiFive RISC-V GPIO Device

2019-05-24T18:58:30+00:00

QEMU model of the GPIO device on the SiFive E300 series SOCs. The pins are not used by a board definition yet, however this implementation can already be used to trigger GPIO interrupts from the software by configuring a pin as both output and input. Signed-off-by: Fabien Chouteau Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt

hw/riscv/Makefile.objs: Create CONFIG_* for riscv boards

2019-02-05T15:50:20+00:00

Add the new configs to default-configs/riscv*-sofmmu.mak. Signed-off-by: Yang Zhong Signed-off-by: Paolo Bonzini Reviewed-by: Alistair Francis Reviewed-by: Thomas Huth Message-Id: <20190202072456.6468-19-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini

RISC-V Build Infrastructure

2018-03-06T19:30:28+00:00

This adds RISC-V into the build system enabling the following targets: - riscv32-softmmu - riscv64-softmmu - riscv32-linux-user - riscv64-linux-user This adds defaults configs for RISC-V, enables the build for the RISC-V CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh' script is updated to add the RISC-V ELF magic. Expected checkpatch errors for consistency reasons: ERROR: line over 90 characters FILE: scripts/qemu-binfmt-conf.sh Reviewed-by: Richard Henderson Signed-off-by: Sagar Karandikar Signed-off-by: Michael Clark