bwlp/qemu.git/hw/riscv, branch spice_video_codecs

riscv: re-randomize rng-seed on reboot

2022-10-27T10:34:31+00:00

When the system reboots, the rng-seed that the FDT has should be re-randomized, so that the new boot gets a new seed. Since the FDT is in the ROM region at this point, we add a hook right after the ROM has been added, so that we have a pointer to that copy of the FDT. Cc: Palmer Dabbelt Cc: Alistair Francis Cc: Bin Meng Cc: qemu-riscv@nongnu.org Signed-off-by: Jason A. Donenfeld Reviewed-by: Alistair Francis Message-id: 20221025004327.568476-6-Jason@zx2c4.com Signed-off-by: Peter Maydell

hw/riscv: set machine->fdt in spike_board_init()

2022-10-17T19:15:10+00:00

This will enable support for the 'dumpdtb' QMP/HMP command for the spike machine. Cc: Palmer Dabbelt Cc: Alistair Francis Cc: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Daniel Henrique Barboza Message-Id: <20220926173855.1159396-16-danielhb413@gmail.com>

hw/riscv: set machine->fdt in sifive_u_machine_init()

2022-10-17T19:15:10+00:00

This will enable support for 'dumpdtb' QMP/HMP command for the sifive_u machine. Cc: Alistair Francis Cc: Bin Meng Cc: Palmer Dabbelt Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Daniel Henrique Barboza Message-Id: <20220926173855.1159396-15-danielhb413@gmail.com>

hw/riscv: virt: Enable booting S-mode firmware from pflash

2022-10-14T04:29:50+00:00

To boot S-mode firmware payload like EDK2 from persistent flash storage, qemu needs to pass the flash address as the next_addr in fw_dynamic_info to the opensbi. When both -kernel and -pflash options are provided in command line, the kernel (and initrd if -initrd) will be copied to fw_cfg table. The S-mode FW will load the kernel/initrd from fw_cfg table. If only pflash is given but not -kernel, then it is the job of of the S-mode firmware to locate and load the kernel. In either case, update the kernel_entry with the flash address so that the opensbi can jump to the entry point of the S-mode firmware. Signed-off-by: Sunil V L Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Message-Id: <20221004092351.18209-4-sunilvl@ventanamicro.com> Signed-off-by: Alistair Francis

hw/riscv: virt: Move create_fw_cfg() prior to loading kernel

2022-10-14T04:29:50+00:00

To enable both -kernel and -pflash options, the fw_cfg needs to be created prior to loading the kernel. Signed-off-by: Sunil V L Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Message-Id: <20221004092351.18209-3-sunilvl@ventanamicro.com> Signed-off-by: Alistair Francis

hw/riscv: Update comment for qtest check in riscv_find_firmware()

2022-10-14T04:29:50+00:00

Since commit 4211fc553234 ("roms/opensbi: Remove ELF images"), the comment for qtest check in riscv_find_firmware() is out of date. Update it to reflect the latest status. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: Signed-off-by: Alistair Francis

hw/riscv: opentitan: Expose the resetvec as a SoC property

2022-09-26T21:04:38+00:00

On the OpenTitan hardware the resetvec is fixed at the start of ROM. In QEMU we don't run the ROM code and instead just jump to the next stage. This means we need to be a little more flexible about what the resetvec is. This patch allows us to set the resetvec from the command line with something like this: -global driver=riscv.lowrisc.ibex.soc,property=resetvec,value=0x20000400 This way as the next stage changes we can update the resetvec. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20220914101108.82571-4-alistair.francis@wdc.com> Signed-off-by: Alistair Francis

hw/riscv: opentitan: Fixup resetvec

2022-09-26T21:04:38+00:00

The resetvec for the OpenTitan machine ended up being set to an out of date value, so let's fix that and bump it to the correct start address (after the boot ROM) Fixes: bf8803c64d75 "hw/riscv: opentitan: bump opentitan version" Signed-off-by: Alistair Francis Message-Id: <20220914101108.82571-3-alistair.francis@wdc.com> Signed-off-by: Alistair Francis

hw/riscv: virt: Add PMU DT node to the device tree

2022-09-07T07:19:15+00:00

Qemu virt machine can support few cache events and cycle/instret counters. It also supports counter overflow for these events. Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine capabilities. There are some dummy nodes added for testing as well. Acked-by: Alistair Francis Signed-off-by: Atish Patra Signed-off-by: Atish Patra Message-Id: <20220824221701.41932-5-atishp@rivosinc.com> Signed-off-by: Alistair Francis

target/riscv: Use official extension names for AIA CSRs

2022-09-07T07:18:33+00:00

The arch review of AIA spec is completed and we now have official extension names for AIA: Smaia (M-mode AIA CSRs) and Ssaia (S-mode AIA CSRs). Refer, section 1.6 of the latest AIA v0.3.1 stable specification at https://github.com/riscv/riscv-aia/releases/download/0.3.1-draft.32/riscv-interrupts-032.pdf) Based on above, we update QEMU RISC-V to: 1) Have separate config options for Smaia and Ssaia extensions which replace RISCV_FEATURE_AIA in CPU features 2) Not generate AIA INTC compatible string in virt machine Signed-off-by: Anup Patel Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Message-id: 20220820042958.377018-1-apatel@ventanamicro.com Signed-off-by: Alistair Francis