bwlp/qemu.git/hw/xtensa/mx_pic.c, branch spice_video_codecsExperimental fork of QEMU with video encoding patcheshttps://git.openslx.org/bwlp/qemu.git/atom/hw/xtensa/mx_pic.c?h=spice_video_codecs2022-05-06T22:27:40+00:00hw/xtensa: fix reset value of MIROUT register of MX PIC2022-05-06T22:27:40+00:00Max Filippov2022-04-26T16:24:01+00:00urn:sha1:c6f3f334d157ff6b9bdc4e1b9d9874234138836a
MX PIC comes out of reset with IRQ routing registers set to 0, thus
not delivering any external IRQ to any connected CPU by default.
Fix the model to match the hardware.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Include hw/hw.h exactly where needed2019-08-16T11:31:52+00:00Markus Armbruster2019-08-12T05:23:48+00:00urn:sha1:650d103d3ea959212f826acb9d3fe80cf30e347b
In my "build everything" tree, changing hw/hw.h triggers a recompile
of some 2600 out of 6600 objects (not counting tests and objects that
don't depend on qemu/osdep.h).
The previous commits have left only the declaration of hw_error() in
hw/hw.h. This permits dropping most of its inclusions. Touching it
now recompiles less than 200 objects.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20190812052359.30071-19-armbru@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Include hw/irq.h a lot less2019-08-16T11:31:52+00:00Markus Armbruster2019-08-12T05:23:42+00:00urn:sha1:64552b6be4758d3a774f7787b294543ccebd5358
In my "build everything" tree, changing hw/irq.h triggers a recompile
of some 5400 out of 6600 objects (not counting tests and objects that
don't depend on qemu/osdep.h).
hw/hw.h supposedly includes it for convenience. Several other headers
include it just to get qemu_irq and.or qemu_irq_handler.
Move the qemu_irq and qemu_irq_handler typedefs from hw/irq.h to
qemu/typedefs.h, and then include hw/irq.h only where it's still
needed. Touching it now recompiles only some 500 objects.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20190812052359.30071-13-armbru@redhat.com>
target/xtensa: add MX interrupt controller2019-01-28T19:55:20+00:00Max Filippov2013-02-17T12:38:58+00:00urn:sha1:10df8ff146ff0219cf746ac13ffa870c4cf0350a
MX interrupt controller is a collection of the following devices
accessible through the external registers interface:
- interrupt distributor can route each external IRQ line to the
corresponding external IRQ pin of selected subset of connected xtensa
cores. It has per-CPU and per-IRQ enable signals and per-IRQ software
assert signals;
- IPI controller has 16 per-CPU IPI signals that may be routed to a
combination of 3 designated external IRQ pins of connected xtensa
cores;
- cache coherecy register controls core L1 cache participation in the
SMP cluster cache coherency protocol;
- runstall register lets BSP core stall and unstall AP cores.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>