bwlp/qemu.git/include/hw/core, branch spice_video_codecs

accel/qtest: Support qtest accelerator for Windows

2022-10-28T09:17:12+00:00

Currently signal SIGIPI [=SIGUSR1] is used to kick the dummy CPU when qtest accelerator is used. However SIGUSR1 is unsupported on Windows. To support Windows, we add a QemuSemaphore CPUState::sem to kick the dummy CPU instead for Windows. Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng Reviewed-by: Marc-André Lureau Message-Id: <20221028045736.679903-2-bin.meng@windriver.com> Signed-off-by: Thomas Huth

accel/tcg: Add restore_state_to_opc to TCGCPUOps

2022-10-26T01:11:28+00:00

Add a tcg_ops hook to replace the restore_state_to_opc function call. Because these generic hooks cannot depend on target-specific types, temporarily, copy the current target_ulong data[] into uint64_t d64[]. Reviewed-by: Claudio Fontana Signed-off-by: Richard Henderson

dump: Replace opaque DumpState pointer with a typed one

2022-10-06T15:30:43+00:00

It's always better to convey the type of a pointer if at all possible. So let's add the DumpState typedef to typedefs.h and move the dump note functions from the opaque pointers to DumpState pointers. Signed-off-by: Janosch Frank CC: Peter Maydell CC: Cédric Le Goater CC: Daniel Henrique Barboza CC: David Gibson CC: Greg Kurz CC: Palmer Dabbelt CC: Alistair Francis CC: Bin Meng CC: Cornelia Huck CC: Thomas Huth CC: Richard Henderson CC: David Hildenbrand Acked-by: Daniel Henrique Barboza Reviewed-by: Marc-André Lureau Message-Id: <20220811121111.9878-2-frankja@linux.ibm.com>

hw/core: Add CPUClass.get_pc

2022-10-04T19:13:12+00:00

Populate this new method for all targets. Always match the result that would be given by cpu_get_tb_cpu_state, as we will want these values to correspond in the logs. Reviewed-by: Taylor Simpson Reviewed-by: Alex Bennée Reviewed-by: Mark Cave-Ayland (target/sparc) Signed-off-by: Richard Henderson --- Cc: Eduardo Habkost (supporter:Machine core) Cc: Marcel Apfelbaum (supporter:Machine core) Cc: "Philippe Mathieu-Daudé" (reviewer:Machine core) Cc: Yanan Wang (reviewer:Machine core) Cc: Michael Rolnik (maintainer:AVR TCG CPUs) Cc: "Edgar E. Iglesias" (maintainer:CRIS TCG CPUs) Cc: Taylor Simpson (supporter:Hexagon TCG CPUs) Cc: Song Gao (maintainer:LoongArch TCG CPUs) Cc: Xiaojuan Yang (maintainer:LoongArch TCG CPUs) Cc: Laurent Vivier (maintainer:M68K TCG CPUs) Cc: Jiaxun Yang (reviewer:MIPS TCG CPUs) Cc: Aleksandar Rikalo (reviewer:MIPS TCG CPUs) Cc: Chris Wulff (maintainer:NiosII TCG CPUs) Cc: Marek Vasut (maintainer:NiosII TCG CPUs) Cc: Stafford Horne (odd fixer:OpenRISC TCG CPUs) Cc: Yoshinori Sato (reviewer:RENESAS RX CPUs) Cc: Mark Cave-Ayland (maintainer:SPARC TCG CPUs) Cc: Bastian Koppelmann (maintainer:TriCore TCG CPUs) Cc: Max Filippov (maintainer:Xtensa TCG CPUs) Cc: qemu-arm@nongnu.org (open list:ARM TCG CPUs) Cc: qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs) Cc: qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Cc: qemu-s390x@nongnu.org (open list:S390 TCG CPUs)

include/hw/core: Create struct CPUJumpCache

2022-10-04T19:13:12+00:00

Wrap the bare TranslationBlock pointer into a structure. Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson

accel/tcg: Drop addr member from SavedIOTLB

2022-10-04T03:53:30+00:00

This field is only written, not read; remove it. Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson

cpu: cache CPUClass in CPUState for hot code paths

2022-10-04T03:53:30+00:00

The class cast checkers are quite expensive and always on (unlike the dynamic case who's checks are gated by CONFIG_QOM_CAST_DEBUG). To avoid the overhead of repeatedly checking something which should never change we cache the CPUClass reference for use in the hot code paths. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20220811151413.3350684-3-alex.bennee@linaro.org> Signed-off-by: Cédric Le Goater Message-Id: <20220923084803.498337-3-clg@kaod.org> Signed-off-by: Richard Henderson

softmmu/dirtylimit: Implement virtual CPU throttle

2022-07-20T11:15:08+00:00

Setup a negative feedback system when vCPU thread handling KVM_EXIT_DIRTY_RING_FULL exit by introducing throttle_us_per_full field in struct CPUState. Sleep throttle_us_per_full microseconds to throttle vCPU if dirtylimit is in service. Signed-off-by: Hyman Huang(黄勇) Reviewed-by: Peter Xu Message-Id: <977e808e03a1cef5151cae75984658b6821be618.1656177590.git.huangy81@chinatelecom.cn> Signed-off-by: Dr. David Alan Gilbert

hw/core: Move the ARM sysbus-fdt to core

2022-04-29T00:48:26+00:00

The ARM virt machine currently uses sysbus-fdt to create device tree entries for dynamically created MMIO devices. The RISC-V virt machine can also benefit from this, so move the code to the core directory. Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Reviewed-by: Bin Meng Message-Id: <20220427234146.1130752-3-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis

hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()

2022-04-22T00:35:16+00:00

This is now used by RISC-V as well. Update the comments. Signed-off-by: Bin Meng Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20220421003324.1134983-7-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis