bwlp/qemu.git/include/hw/gpio, branch spice_video_codecs

hw/gpio: replace HWADDR_PRIx with PRIx64

2022-05-25T08:31:33+00:00

1. replace HWADDR_PRIx with PRIx64 2. fix indent issue Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater Message-Id: <20220525053444.27228-5-jamin_lin@aspeedtech.com> Signed-off-by: Cédric Le Goater

hw/gpio support GPIO index mode for write operation.

2022-05-25T08:31:33+00:00

It did not support GPIO index mode for read operation. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater Message-Id: <20220525053444.27228-4-jamin_lin@aspeedtech.com> Signed-off-by: Cédric Le Goater

Clean up decorations and whitespace around header guards

2022-05-11T14:50:32+00:00

Cleaned up with scripts/clean-header-guards.pl. Signed-off-by: Markus Armbruster Message-Id: <20220506134911.2856099-5-armbru@redhat.com> Reviewed-by: Richard Henderson

hw: aspeed_gpio: Fix GPIO array indexing

2021-10-12T06:20:08+00:00

The gpio array is declared as a dense array: qemu_irq gpios[ASPEED_GPIO_NR_PINS]; (AST2500 has 228, AST2400 has 216, AST2600 has 208) However, this array is used like a matrix of GPIO sets (e.g. gpio[NR_SETS][NR_PINS_PER_SET] = gpio[8][32]) size_t offset = set * GPIOS_PER_SET + gpio; qemu_set_irq(s->gpios[offset], !!(new & mask)); This can result in an out-of-bounds access to "s->gpios" because the gpio sets do _not_ have the same length. Some of the groups (e.g. GPIOAB) only have 4 pins. 228 != 8 * 32 == 256. To fix this, I converted the gpio array from dense to sparse, to that match both the hardware layout and this existing indexing code. Fixes: 4b7f956862dc2db4c5c ("hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500") Signed-off-by: Peter Delevoryas Message-Id: <20211008033501.934729-2-pdel@fb.com> Signed-off-by: Cédric Le Goater

hw/gpio: Add GPIO model for Nuvoton NPCM7xx

2020-10-27T11:10:32+00:00

The NPCM7xx chips have multiple GPIO controllers that are mostly identical except for some minor differences like the reset values of some registers. Each controller controls up to 32 pins. Each individual pin is modeled as a pair of unnamed GPIOs -- one for emitting the actual pin state, and one for driving the pin externally. Like the nRF51 GPIO controller, a gpio level may be negative, which means the pin is not driven, or floating. Reviewed-by: Tyrone Ting Signed-off-by: Havard Skinnemoen Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell

Use OBJECT_DECLARE_SIMPLE_TYPE when possible

2020-09-18T18:12:32+00:00

This converts existing DECLARE_INSTANCE_CHECKER usage to OBJECT_DECLARE_SIMPLE_TYPE when possible. $ ./scripts/codeconverter/converter.py -i \ --pattern=AddObjectDeclareSimpleType $(git grep -l '' -- '*.[ch]') Signed-off-by: Eduardo Habkost Acked-by: Paul Durrant Message-Id: <20200916182519.415636-6-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost

Use OBJECT_DECLARE_TYPE when possible

2020-09-18T18:12:32+00:00

This converts existing DECLARE_OBJ_CHECKERS usage to OBJECT_DECLARE_TYPE when possible. $ ./scripts/codeconverter/converter.py -i \ --pattern=AddObjectDeclareType $(git grep -l '' -- '*.[ch]') Signed-off-by: Eduardo Habkost Reviewed-by: Cédric Le Goater Acked-by: Paul Durrant Message-Id: <20200916182519.415636-5-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost

sifive: Use DECLARE_CHECKER macros

2020-09-18T17:49:48+00:00

$ ./scripts/codeconverter/converter.py -i \ --pattern=TypeCheckMacro $(git grep -l '' -- '*.[ch]') Signed-off-by: Eduardo Habkost Reviewed-by: Daniel P. Berrangé Message-Id: <20200831210740.126168-12-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost

sifive: Move QOM typedefs and add missing includes

2020-09-18T17:49:48+00:00

Some typedefs and macros are defined after the type check macros. This makes it difficult to automatically replace their definitions with OBJECT_DECLARE_TYPE. Patch generated using: $ ./scripts/codeconverter/converter.py -i \ --pattern=QOMStructTypedefSplit $(git grep -l '' -- '*.[ch]') which will split "typdef struct { ... } TypedefName" declarations. Followed by: $ ./scripts/codeconverter/converter.py -i --pattern=MoveSymbols \ $(git grep -l '' -- '*.[ch]') which will: - move the typedefs and #defines above the type check macros - add missing #include "qom/object.h" lines if necessary Signed-off-by: Eduardo Habkost Reviewed-by: Daniel P. Berrangé Message-Id: <20200831210740.126168-9-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost

Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200910' into staging

2020-09-13T19:29:35+00:00

This PR includes multiple fixes and features for RISC-V: - Fixes a bug in printing trap causes - Allows 16-bit writes to the SiFive test device. This fixes the failure to reboot the RISC-V virt machine - Support for the Microchip PolarFire SoC and Icicle Kit - A reafactor of RISC-V code out of hw/riscv # gpg: Signature made Thu 10 Sep 2020 19:08:06 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis " [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20200910: (30 commits) hw/riscv: Sort the Kconfig options in alphabetical order hw/riscv: Drop CONFIG_SIFIVE hw/riscv: Always build riscv_hart.c hw/riscv: Move sifive_test model to hw/misc hw/riscv: Move sifive_uart model to hw/char hw/riscv: Move riscv_htif model to hw/char hw/riscv: Move sifive_plic model to hw/intc hw/riscv: Move sifive_clint model to hw/intc hw/riscv: Move sifive_gpio model to hw/gpio hw/riscv: Move sifive_u_otp model to hw/misc hw/riscv: Move sifive_u_prci model to hw/misc hw/riscv: Move sifive_e_prci model to hw/misc hw/riscv: sifive_u: Connect a DMA controller hw/riscv: clint: Avoid using hard-coded timebase frequency hw/riscv: microchip_pfsoc: Hook GPIO controllers hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 hw/net: cadence_gem: Add a new 'phy-addr' property hw/riscv: microchip_pfsoc: Connect a DMA controller hw/dma: Add SiFive platform DMA controller emulation ... Signed-off-by: Peter Maydell # Conflicts: # hw/riscv/trace-events

bwlp/qemu.git/include/hw/gpio, branch spice_video_codecs

hw/gpio: replace HWADDR_PRIx with PRIx64

hw/gpio support GPIO index mode for write operation.

Clean up decorations and whitespace around header guards

hw: aspeed_gpio: Fix GPIO array indexing

hw/gpio: Add GPIO model for Nuvoton NPCM7xx

Use OBJECT_DECLARE_SIMPLE_TYPE when possible

Use OBJECT_DECLARE_TYPE when possible

sifive: Use DECLARE_*CHECKER* macros

sifive: Move QOM typedefs and add missing includes

Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200910' into staging

sifive: Use DECLARE_CHECKER macros