bwlp/qemu.git/include/hw/misc, branch spice_video_codecs

hw/ppc/mac.h: Rename to include/hw/nvram/mac_nvram.h

2022-10-31T18:48:23+00:00

All that is left in mac.h now belongs to the nvram emulation so rename it accordingly and only include it where it is really used. Signed-off-by: BALATON Zoltan Reviewed-by: Mark Cave-Ayland Message-Id: Signed-off-by: Mark Cave-Ayland

hw/ppc/mac.h: Move macio specific parts out from shared header

2022-10-31T18:48:23+00:00

Move the parts specific to and only used by macio out from the shared mac.h into macio.c where they better belong. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Mark Cave-Ayland Message-Id: Signed-off-by: Mark Cave-Ayland

aspeed: sbc: Allow per-machine settings

2022-07-14T14:24:38+00:00

In order to correctly report secure boot running firmware the values of certain registers must be set. We don't yet have documentation from ASPEED on what they mean. The meaning is inferred from u-boot's use of them. Introduce properties so the settings can be configured per-machine. Reviewed-by: Peter Delevoryas Tested-by: Peter Delevoryas Signed-off-by: Joel Stanley Message-Id: <20220628154740.1117349-4-clg@kaod.org> Signed-off-by: Cédric Le Goater

hw/misc/aspeed: Add PECI controller

2022-06-30T07:21:14+00:00

This introduces a really basic PECI controller that responses to commands by always setting the response code to success and then raising an interrupt to indicate the command is done. This helps avoid getting hit with constant errors if the driver continuously attempts to send a command and keeps timing out. The AST2400 and AST2500 only included registers up to 0x5C, not 0xFC. They supported PECI 1.1, 2.0, and 3.0. The AST2600 and AST1030 support PECI 4.0, which includes more read/write buffer registers from 0x80 to 0xFC to support 64-byte mode. This patch doesn't attempt to handle that, or to create a different version of the controller for the different generations, since it's only implementing functionality that is common to all generations. The basic sequence of events is that the firmware will read and write to various registers and then trigger a command by setting the FIRE bit in the command register (similar to the I2C controller). Then the firmware waits for an interrupt from the PECI controller, expecting the interrupt status register to be filled in with info on what happened. If the command was transmitted and received successfully, then response codes from the host CPU will be found in the data buffer registers. Signed-off-by: Peter Delevoryas Reviewed-by: Cédric Le Goater Message-Id: <20220630045133.32251-12-me@pjd.dev> [ clg: s/sysbus_mmio_map/aspeed_mmio_map/ ] Signed-off-by: Cédric Le Goater

acpi: pvpanic-isa: use AcpiDevAmlIfClass:build_dev_aml to provide device's AML

2022-06-09T23:32:49+00:00

.. and clean up not longer needed conditionals in DSTD build code pvpanic-isa AML will be fetched and included when ISA bridge will build its own AML code (including attached devices). Expected AML change: the device under separate _SB.PCI0.ISA scope is moved directly under Device(ISA) node. Signed-off-by: Igor Mammedov Acked-by: Gerd Hoffmann Message-Id: <20220608135340.3304695-29-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin

Clean up decorations and whitespace around header guards

2022-05-11T14:50:32+00:00

Cleaned up with scripts/clean-header-guards.pl. Signed-off-by: Markus Armbruster Message-Id: <20220506134911.2856099-5-armbru@redhat.com> Reviewed-by: Richard Henderson

Clean up header guards that don't match their file name

2022-05-11T14:49:06+00:00

Header guard symbols should match their file name to make guard collisions less likely. Cleaned up with scripts/clean-header-guards.pl, followed by some renaming of new guard symbols picked by the script to better ones. Signed-off-by: Markus Armbruster Message-Id: <20220506134911.2856099-2-armbru@redhat.com> Reviewed-by: Richard Henderson [Change to generated file ebpf/rss.bpf.skeleton.h backed out]

lasi: move from hw/hppa to hw/misc

2022-05-08T17:52:37+00:00

Move the LASI device implementation from hw/hppa to hw/misc so that it is located with all the other miscellaneous devices. Signed-off-by: Mark Cave-Ayland Acked-by: Helge Deller Message-Id: <20220504092600.10048-43-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland

aspeed/hace: Support AST1030 HACE

2022-05-03T05:17:20+00:00

Per ast1030_v7.pdf, AST1030 HACE engine is identical to AST2600's HACE engine. Signed-off-by: Steven Lee Signed-off-by: Cédric Le Goater

aspeed/hace: Support AST2600 HACE

2022-05-02T15:03:04+00:00

The aspeed ast2600 accumulative mode is described in datasheet ast2600v10.pdf section 25.6.4: 1. Allocating and initiating accumulative hash digest write buffer with initial state. * Since QEMU crypto/hash api doesn't provide the API to set initial state of hash library, and the initial state is already set by crypto library (gcrypt/glib/...), so skip this step. 2. Calculating accumulative hash digest. (a) When receiving the last accumulative data, software need to add padding message at the end of the accumulative data. Padding message described in specific of MD5, SHA-1, SHA224, SHA256, SHA512, SHA512/224, SHA512/256. * Since the crypto library (gcrypt/glib) already pad the padding message internally. * This patch is to remove the padding message which fed byguest machine driver. Signed-off-by: Troy Lee Signed-off-by: Steven Lee Reviewed-by: Cédric Le Goater Message-Id: <20220426021120.28255-3-steven_lee@aspeedtech.com> Signed-off-by: Cédric Le Goater