<feed xmlns='http://www.w3.org/2005/Atom'>
<title>bwlp/qemu.git/include/hw/ppc, branch spice_video_codecs</title>
<subtitle>Experimental fork of QEMU with video encoding patches</subtitle>
<id>https://git.openslx.org/bwlp/qemu.git/atom/include/hw/ppc?h=spice_video_codecs</id>
<link rel='self' href='https://git.openslx.org/bwlp/qemu.git/atom/include/hw/ppc?h=spice_video_codecs'/>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/'/>
<updated>2022-10-28T16:15:23+00:00</updated>
<entry>
<title>ppc4xx_sdram: Move ppc4xx_sdram_banks() to ppc4xx_sdram.c</title>
<updated>2022-10-28T16:15:23+00:00</updated>
<author>
<name>BALATON Zoltan</name>
</author>
<published>2022-10-19T16:02:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=080741abc293e79b6e860e2c8d66bfe519090c86'/>
<id>urn:sha1:080741abc293e79b6e860e2c8d66bfe519090c86</id>
<content type='text'>
This function is only used by the ppc4xx memory controller models so
it can be made static.

Signed-off-by: BALATON Zoltan &lt;balaton@eik.bme.hu&gt;
Reviewed-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
Message-Id: &lt;b1504a82157a586aa284e8ee3b427b9a07b24169.1666194485.git.balaton@eik.bme.hu&gt;
Signed-off-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
</content>
</entry>
<entry>
<title>ppc440_uc.c: Move some macros to ppc4xx.h</title>
<updated>2022-10-17T19:15:09+00:00</updated>
<author>
<name>BALATON Zoltan</name>
</author>
<published>2022-09-24T12:28:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=2196d337c553a17b1578ada42ab24adaca579ab7'/>
<id>urn:sha1:2196d337c553a17b1578ada42ab24adaca579ab7</id>
<content type='text'>
These are used by both the SDRAM controller model and system DCRs. In
preparation to move SDRAM controller in its own file move these macros
to the ppc4xx.h header.

Signed-off-by: BALATON Zoltan &lt;balaton@eik.bme.hu&gt;
Reviewed-by: Cédric Le Goater &lt;clg@kaod.org&gt;
Message-Id: &lt;74d9bf4891e2ccceb52bb6ca6b54fd3f37a9fb04.1664021647.git.balaton@eik.bme.hu&gt;
Signed-off-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
</content>
</entry>
<entry>
<title>ppc440_sdram: QOM'ify</title>
<updated>2022-10-17T19:15:09+00:00</updated>
<author>
<name>BALATON Zoltan</name>
</author>
<published>2022-09-24T12:28:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=5f7effe4df91702add08e3e3dc1871fd35a8903f'/>
<id>urn:sha1:5f7effe4df91702add08e3e3dc1871fd35a8903f</id>
<content type='text'>
Change the ppc440_sdram model to a QOM class derived from the
PPC4xx-dcr-device and name it ppc4xx-sdram-ddr2. This is mostly
modelling the DDR2 SDRAM controller found in the 460EX (used on the
sam460ex board). Newer SoCs (regardless of their PPC core, e.g. 405EX)
may have this controller but we only emulate enough of it for the
sam460ex u-boot firmware.

Signed-off-by: BALATON Zoltan &lt;balaton@eik.bme.hu&gt;
Reviewed-by: Cédric Le Goater &lt;clg@kaod.org&gt;
Message-Id: &lt;3e82ae575c7c41e464a0082d55ecb4ebcc4d4329.1664021647.git.balaton@eik.bme.hu&gt;
Signed-off-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
</content>
</entry>
<entry>
<title>ppc4xx_sdram: Rename functions to prevent name clashes</title>
<updated>2022-10-17T19:15:09+00:00</updated>
<author>
<name>BALATON Zoltan</name>
</author>
<published>2022-09-24T12:28:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=1e545fbc88bb5abe21553972a2244f272153476d'/>
<id>urn:sha1:1e545fbc88bb5abe21553972a2244f272153476d</id>
<content type='text'>
Rename functions to avoid name clashes when moving the DDR2 controller
model currently called ppc440_sdram to ppc4xx_devs. This also more
clearly shows which function belongs to which model.

Signed-off-by: BALATON Zoltan &lt;balaton@eik.bme.hu&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Message-Id: &lt;9c09d10fbf36940ebbe30d7038d69cf3f2e58371.1664021647.git.balaton@eik.bme.hu&gt;
Signed-off-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
</content>
</entry>
<entry>
<title>ppc440_sdram: Get rid of the init RAM hack</title>
<updated>2022-10-17T19:15:09+00:00</updated>
<author>
<name>BALATON Zoltan</name>
</author>
<published>2022-09-24T12:28:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=03f7041bfdc45f6c981a83fd2d932bad161769ad'/>
<id>urn:sha1:03f7041bfdc45f6c981a83fd2d932bad161769ad</id>
<content type='text'>
Remove the do_init parameter of ppc440_sdram_init and enable SDRAM
controller from the board. Firmware does this so it may only be needed
when booting with -kernel without firmware but we enable SDRAM
unconditionally to preserve previous behaviour.

Signed-off-by: BALATON Zoltan &lt;balaton@eik.bme.hu&gt;
Reviewed-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
Message-Id: &lt;c2eda8f83c82f655aa7821a5a8c9310484bd6a1d.1664021647.git.balaton@eik.bme.hu&gt;
Signed-off-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
</content>
</entry>
<entry>
<title>ppc4xx_sdram: QOM'ify</title>
<updated>2022-10-17T19:15:09+00:00</updated>
<author>
<name>BALATON Zoltan</name>
</author>
<published>2022-09-24T12:27:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=4fc30e153a0fbb11bd6826cf67d52b1d9122bac3'/>
<id>urn:sha1:4fc30e153a0fbb11bd6826cf67d52b1d9122bac3</id>
<content type='text'>
Change the ppc4xx_sdram model to a QOM class derived from the
PPC4xx-dcr-device and name it ppc4xx-sdram-ddr. This is mostly
modelling the DDR SDRAM controller found in the 440EP (used on the
bamboo board) but also backward compatible with the older DDR
controllers on some 405 SoCs so we also use it for those now. This
likely does not cause problems for guests we run as the new features
are just not accessed but to model 405 SoC accurately some features
may have to be disabled or the model split between 440 and older.

Newer SoCs (regardless of their PPC core, e.g. 405EX) may have an
updated DDR2 SDRAM controller implemented by the ppc440_sdram model
(only partially, enough for the 460EX on the sam460ex) that is not yet
QOM'ified in this patch. That is intended to become ppc4xx-sdram-ddr2
when QOM'ified later.

Signed-off-by: BALATON Zoltan &lt;balaton@eik.bme.hu&gt;
Reviewed-by: Cédric Le Goater &lt;clg@kaod.org&gt;
Message-Id: &lt;8f820487fc9011343032c422ecdf3e8ee74d8c11.1664021647.git.balaton@eik.bme.hu&gt;
Signed-off-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
</content>
</entry>
<entry>
<title>ppc4xx_sdram: Move size check to ppc4xx_sdram_init()</title>
<updated>2022-10-17T19:15:09+00:00</updated>
<author>
<name>BALATON Zoltan</name>
</author>
<published>2022-09-24T12:27:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=0aedcc8a8db88967d3abbff433bdd1f5a4b9ce6d'/>
<id>urn:sha1:0aedcc8a8db88967d3abbff433bdd1f5a4b9ce6d</id>
<content type='text'>
Instead of checking if memory size is valid in board code move this
check to ppc4xx_sdram_init() as this is a restriction imposed by the
SDRAM controller.

Signed-off-by: BALATON Zoltan &lt;balaton@eik.bme.hu&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Message-Id: &lt;39e5129dd095b285676a6267c5753786da1bc30d.1664021647.git.balaton@eik.bme.hu&gt;
Signed-off-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
</content>
</entry>
<entry>
<title>ppc4xx: Use Ppc4xxSdramBank in ppc4xx_sdram_banks()</title>
<updated>2022-10-17T19:15:09+00:00</updated>
<author>
<name>BALATON Zoltan</name>
</author>
<published>2022-09-24T12:27:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=734c44ea13272c3b3d5cd9345cc4df7ce9bd30b3'/>
<id>urn:sha1:734c44ea13272c3b3d5cd9345cc4df7ce9bd30b3</id>
<content type='text'>
Change ppc4xx_sdram_banks() to take one Ppc4xxSdramBank array instead
of the separate arrays and adjust ppc4xx_sdram_init() and
ppc440_sdram_init() accordingly as well as machines using these.

Signed-off-by: BALATON Zoltan &lt;balaton@eik.bme.hu&gt;
Reviewed-by: Cédric Le Goater &lt;clg@kaod.org&gt;
Message-Id: &lt;e3a1fea51f29779fd6a61be90a29c684f3299544.1664021647.git.balaton@eik.bme.hu&gt;
Signed-off-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
</content>
</entry>
<entry>
<title>ppc4xx_sdram: Get rid of the init RAM hack</title>
<updated>2022-10-17T19:15:09+00:00</updated>
<author>
<name>BALATON Zoltan</name>
</author>
<published>2022-09-24T12:27:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=68b9a2e38d7183f64dddc5faec9a16c70a4f095c'/>
<id>urn:sha1:68b9a2e38d7183f64dddc5faec9a16c70a4f095c</id>
<content type='text'>
The do_init parameter of ppc4xx_sdram_init() is used to map memory
regions that is normally done by the firmware by programming the SDRAM
controller. Do this from board code emulating what firmware would do
when booting a kernel directly from -kernel without a firmware so we
can get rid of this do_init hack.

Signed-off-by: BALATON Zoltan &lt;balaton@eik.bme.hu&gt;
Reviewed-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
Message-Id: &lt;d6c44c870befa1a075e21f1a59926dcdaff63f6b.1664021647.git.balaton@eik.bme.hu&gt;
Signed-off-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
</content>
</entry>
<entry>
<title>ppc4xx: Introduce Ppc4xxSdramBank struct</title>
<updated>2022-10-17T19:15:09+00:00</updated>
<author>
<name>BALATON Zoltan</name>
</author>
<published>2022-09-24T12:27:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=8626982301dc8dbbe49e0fb1730461955df879c8'/>
<id>urn:sha1:8626982301dc8dbbe49e0fb1730461955df879c8</id>
<content type='text'>
Instead of storing sdram bank parameters in unrelated arrays put them
in a struct so it's clear they belong to the same bank and simplify
the state struct using this bank type.

Signed-off-by: BALATON Zoltan &lt;balaton@eik.bme.hu&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Message-Id: &lt;5eb82d0424c584b2b9e6f7bc51560f8189ed21bb.1664021647.git.balaton@eik.bme.hu&gt;
Signed-off-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
</content>
</entry>
</feed>
