bwlp/qemu.git/include/hw/sd, branch spice_video_codecs

hw/sd: Fix sun4i allwinner-sdhost for U-Boot

2022-11-21T11:45:12+00:00

Trying to run U-Boot for Cubieboard (Allwinner A10) fails because it cannot access SD card. The problem is that FIFO register in current allwinner-sdhost implementation is at the address corresponding to Allwinner H3, but not A10. Linux kernel is not affected since Linux driver uses DMA access and does not use FIFO register for reading/writing. This patch adds new class parameter `is_sun4i` and based on that parameter uses register at offset 0x100 either as FIFO register (if sun4i) or as threshold register (if not sun4i; in this case register at 0x200 is FIFO register). Tested with U-Boot and Linux kernel image built for Cubieboard and OrangePi PC. Signed-off-by: Strahinja Jankovic Reviewed-by: Peter Maydell Message-id: 20221112214900.24152-1-strahinja.p.jankovic@gmail.com Signed-off-by: Peter Maydell

hw/sd: add nuvoton MMC

2021-11-02T18:14:55+00:00

Signed-off-by: Shengtan Mao Signed-off-by: Hao Wu Reviewed-by: Hao Wu Reviewed-by: Chris Rauer Reviewed-by: Tyrone Ting Reviewed-by: Peter Maydell Message-Id: <20211008002628.1958285-2-wuhaotsh@google.com> [rth: Fix typos of "nonexistent"] Signed-off-by: Richard Henderson

Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.0-pull-request' into staging

2021-02-21T12:12:18+00:00

Pull request trivial patches 20210220 # gpg: Signature made Sat 20 Feb 2021 12:34:21 GMT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier " [full] # gpg: aka "Laurent Vivier " [full] # gpg: aka "Laurent Vivier (Red Hat) " [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-for-6.0-pull-request: MAINTAINERS: Fix default-configs/ entries target/avr/cpu: Use device_class_set_parent_realize() hw/scsi/megasas: Remove pointless parenthesis u2f-passthru: put it into the 'misc' category tpm: put some tpm devices into the correct category nvdimm: put it into the 'storage' category vmmouse: put it into the 'input' category virtio-pmem: put it into the 'storage' category MAINTAINERS: add my github tree URL Fix SPDX-License-Identifier typos hw/block/fdc: Remove the check_media_rate property hw/i386/xen: Remove dead code Signed-off-by: Peter Maydell

Fix SPDX-License-Identifier typos

2021-02-20T11:36:19+00:00

Several SPDX headers contain "SPDX-License-Identifer" (note the missing "i" before "er"); fix these typos. Signed-off-by: Ryan Finnie Cc: qemu-trivial@nongnu.org Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210201200147.211914-1-ryan@finnie.org> Signed-off-by: Laurent Vivier

hw/sd: Introduce receive_ready() callback

2021-02-19T23:17:09+00:00

At present there is a data_ready() callback for the SD data read path. Let's add a receive_ready() for the SD data write path. Signed-off-by: Bin Meng Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis Message-Id: <20210128063035.15674-5-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé

hw/sd: sd.h: Cosmetic change of using spaces

2021-01-24T19:11:05+00:00

QEMU coding convention prefers spaces over tabs. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210123104016.17485-15-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé

Use OBJECT_DECLARE_SIMPLE_TYPE when possible

2020-09-18T18:12:32+00:00

This converts existing DECLARE_INSTANCE_CHECKER usage to OBJECT_DECLARE_SIMPLE_TYPE when possible. $ ./scripts/codeconverter/converter.py -i \ --pattern=AddObjectDeclareSimpleType $(git grep -l '' -- '*.[ch]') Signed-off-by: Eduardo Habkost Acked-by: Paul Durrant Message-Id: <20200916182519.415636-6-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost

Use OBJECT_DECLARE_TYPE when possible

2020-09-18T18:12:32+00:00

This converts existing DECLARE_OBJ_CHECKERS usage to OBJECT_DECLARE_TYPE when possible. $ ./scripts/codeconverter/converter.py -i \ --pattern=AddObjectDeclareType $(git grep -l '' -- '*.[ch]') Signed-off-by: Eduardo Habkost Reviewed-by: Cédric Le Goater Acked-by: Paul Durrant Message-Id: <20200916182519.415636-5-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost

qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros

2020-09-18T18:12:32+00:00

One of the goals of having less boilerplate on QOM declarations is to avoid human error. Requiring an extra argument that is never used is an opportunity for mistakes. Remove the unused argument from OBJECT_DECLARE_TYPE and OBJECT_DECLARE_SIMPLE_TYPE. Coccinelle patch used to convert all users of the macros: @@ declarer name OBJECT_DECLARE_TYPE; identifier InstanceType, ClassType, lowercase, UPPERCASE; @@ OBJECT_DECLARE_TYPE(InstanceType, ClassType, - lowercase, UPPERCASE); @@ declarer name OBJECT_DECLARE_SIMPLE_TYPE; identifier InstanceType, lowercase, UPPERCASE; @@ OBJECT_DECLARE_SIMPLE_TYPE(InstanceType, - lowercase, UPPERCASE); Signed-off-by: Eduardo Habkost Reviewed-by: Cédric Le Goater Acked-by: Cornelia Huck Acked-by: Igor Mammedov Acked-by: Paul Durrant Acked-by: Thomas Huth Message-Id: <20200916182519.415636-4-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost

Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200910' into staging

2020-09-13T19:29:35+00:00

This PR includes multiple fixes and features for RISC-V: - Fixes a bug in printing trap causes - Allows 16-bit writes to the SiFive test device. This fixes the failure to reboot the RISC-V virt machine - Support for the Microchip PolarFire SoC and Icicle Kit - A reafactor of RISC-V code out of hw/riscv # gpg: Signature made Thu 10 Sep 2020 19:08:06 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis " [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20200910: (30 commits) hw/riscv: Sort the Kconfig options in alphabetical order hw/riscv: Drop CONFIG_SIFIVE hw/riscv: Always build riscv_hart.c hw/riscv: Move sifive_test model to hw/misc hw/riscv: Move sifive_uart model to hw/char hw/riscv: Move riscv_htif model to hw/char hw/riscv: Move sifive_plic model to hw/intc hw/riscv: Move sifive_clint model to hw/intc hw/riscv: Move sifive_gpio model to hw/gpio hw/riscv: Move sifive_u_otp model to hw/misc hw/riscv: Move sifive_u_prci model to hw/misc hw/riscv: Move sifive_e_prci model to hw/misc hw/riscv: sifive_u: Connect a DMA controller hw/riscv: clint: Avoid using hard-coded timebase frequency hw/riscv: microchip_pfsoc: Hook GPIO controllers hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 hw/net: cadence_gem: Add a new 'phy-addr' property hw/riscv: microchip_pfsoc: Connect a DMA controller hw/dma: Add SiFive platform DMA controller emulation ... Signed-off-by: Peter Maydell # Conflicts: # hw/riscv/trace-events