bwlp/qemu.git/include/tcg, branch master

accel/tcg: Introduce tb_pc and log_pc

2022-10-04T19:13:12+00:00

The availability of tb->pc will shortly be conditional. Introduce accessor functions to minimize ifdefs. Pass around a known pc to places like tcg_gen_code, where the caller must already have the value. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson

tcg: Add tcg_gen_mov_ptr

2022-06-02T15:09:46+00:00

Add an interface to perform moves between TCGv_ptr. Reviewed-by: Matheus Ferst Signed-off-by: Richard Henderson

Normalize header guard symbol definition

2022-05-11T14:50:26+00:00

We commonly define the header guard symbol without an explicit value. Normalize the exceptions. Done with scripts/clean-header-guards.pl. Signed-off-by: Markus Armbruster Message-Id: <20220506134911.2856099-4-armbru@redhat.com> Reviewed-by: Richard Henderson

tcg: Implement tcg_gen_{h,w}swap_{i32,i64}

2022-05-04T06:47:19+00:00

Swap half-words (16-bit) and words (32-bit) within a larger value. Mirrors functions of the same names within include/qemu/bitops.h. Signed-off-by: Richard Henderson Signed-off-by: David Hildenbrand Reviewed-by: David Miller Reviewed-by: David Hildenbrand Message-Id: <20220428094708.84835-5-david@redhat.com> Signed-off-by: Thomas Huth

compiler.h: replace QEMU_NORETURN with G_NORETURN

2022-04-21T13:03:51+00:00

G_NORETURN was introduced in glib 2.68, fallback to G_GNUC_NORETURN in glib-compat. Note that this attribute must be placed before the function declaration (bringing a bit of consistency in qemu codebase usage). Signed-off-by: Marc-André Lureau Reviewed-by: Daniel P. Berrangé Reviewed-by: Warner Losh Message-Id: <20220420132624.2439741-20-marcandre.lureau@redhat.com>

tcg: Add tcg_constant_ptr

2022-04-20T19:12:47+00:00

Similar to tcg_const_ptr, defer to tcg_constant_{i32,i64}. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson

tcg: Fix indirect lowering vs TCG_OPF_COND_BRANCH

2022-04-20T19:12:47+00:00

With TCG_OPF_COND_BRANCH, we extended the lifetimes of globals across extended basic blocks. This means that the liveness computed in pass 1 does not kill globals in the same way as normal temps. Introduce TYPE_EBB to match this lifetime, so that we get correct register allocation for the temps that we introduce during the indirect lowering pass. Reviewed-by: Peter Maydell Fixes: b4cb76e6208 ("tcg: Do not kill globals at conditional branches") Signed-off-by: Richard Henderson

tcg: Add opcodes for vector nand, nor, eqv

2022-03-04T18:50:41+00:00

We've had placeholders for these opcodes for a while, and should have support on ppc, s390x and avx512 hosts. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson

tcg: Set MAX_OPC_PARAM_IARGS to 7

2022-03-04T18:50:41+00:00

The last entry of DEF_HELPERS_FLAGS_n is DEF_HELPER_FLAGS_7 and thus the MAX_OPC_PARAM_IARGS should be 7. Reviewed-by: Taylor Simpson Signed-off-by: Ziqiao Kong Message-Id: <20220227113127.414533-2-ziqiaokong@gmail.com> Fixes: e6cadf49c3d ("tcg: Add support for a helper with 7 arguments") Signed-off-by: Richard Henderson

tcg/tcg-op-gvec.c: Introduce tcg_gen_gvec_4i

2022-03-02T05:51:38+00:00

Following the implementation of tcg_gen_gvec_3i, add a four-vector and immediate operand expansion method. Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst Message-Id: <20220225210936.1749575-34-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater