Experimental fork of QEMU with video encoding patches https://git.openslx.org/bwlp/qemu.git/atom/linux-user/aarch64/target_cpu.h?h=spice_video_codecs 2022-07-11T12:43:51+00:00 2022-07-11T12:43:51+00:00 Richard Henderson 2022-07-08T15:15:28+00:00 urn:sha1:95aa4fdd58c50ba1d800bb106d73ef8a656e016e Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-34-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> 2020-11-15T15:41:26+00:00 Chetan Pant 2020-10-23T12:24:55+00:00 urn:sha1:1c79145f12a21e129163eee9ca7a2234e2d97751 There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Message-Id: <20201023122455.19417-1-chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> 2019-11-06T12:43:25+00:00 Richard Henderson 2019-11-06T11:33:16+00:00 urn:sha1:07a6ecf48feaddb4914ca8ec9603021f992ec3b9 We will need a target-specific hook for adjusting registers in the parent during clone. Add an empty inline function for each target, and invoke it from the proper places. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20191106113318.10226-11-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu> 2019-11-06T12:42:34+00:00 Richard Henderson 2019-11-06T11:33:15+00:00 urn:sha1:608999d17c8726eb4cfa967e95f06cf026a4dde2 We will need a target-specific hook for adjusting registers in the parent during clone. To avoid confusion, rename the one we have to make it clear it affects the child. At the same time, pass in the flags from the clone syscall. We will need them for correct behaviour for Sparc. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20191106113318.10226-10-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu> 2018-06-03T23:30:44+00:00 Laurent Vivier 2018-05-29T19:42:00+00:00 urn:sha1:9850f9f63acb44724138a2b89b07ea4f6b3d2ba0 Remove useless includes Fix HPPA include guard. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180529194207.31503-9-laurent@vivier.eu> 2016-07-12T14:19:16+00:00 Markus Armbruster 2016-06-29T14:05:18+00:00 urn:sha1:55c5063c61e030c533b4bca8ef2a2ad26f1bc73a These headers all use TARGET_CPU_H as header guard symbol. Reuse of the same guard symbol in multiple headers is okay as long as they cannot be included together. Since we can avoid guard symbol reuse easily, do so: use guard symbol $target_TARGET_CPU_H for linux-user/$target/target_cpu.h. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net> 2014-12-11T12:07:52+00:00 Fabian Aggeler 2014-12-11T12:07:52+00:00 urn:sha1:54bf36ed351c526cde0c853079f9ff1ab7e2ff89 When EL3 is running in AArch32 (or ARMv7 with Security Extensions) FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure and a non-secure instance. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-25-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> 2014-01-07T19:17:59+00:00 Peter Maydell 2014-01-04T22:15:45+00:00 urn:sha1:e4fe830b50b56561dae5b5c79c6eb63cc2e94a3d The common pattern for system registers in a 64-bit capable ARM CPU is that when in AArch32 the cp15 register is a view of the bottom 32 bits of the 64-bit AArch64 system register; writes in AArch32 leave the top half unchanged. The most natural way to model this is to have the state field in the CPU struct be a 64 bit value, and simply have the AArch32 TCG code operate on a pointer to its lower half. For aarch64-linux-user the only registers we need to share like this are the thread-local-storage ones. Widen their fields to 64 bits and provide the 64 bit reginfo struct to make them visible in AArch64 state. Note that minor cleanup of the AArch64 system register encoding space means We can share the TPIDR_EL1 reginfo but need split encodings for TPIDR_EL0 and TPIDRRO_EL0. Since we're touching almost every line in QEMU that uses the c13_tls* fields in this patch anyway, we take the opportunity to rename them in line with the standard ARM architectural names for these registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> 2013-09-10T18:11:29+00:00 Alexander Graf 2013-09-03T19:12:18+00:00 urn:sha1:e2cea499cc2e8da5b2d5753625d2c57685193783 Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-19-git-send-email-peter.maydell@linaro.org [PMM: pulled out from another patch; don't use is_a64() here; moved to linux-user from target-arm] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>