Experimental fork of QEMU with video encoding patches https://git.openslx.org/bwlp/qemu.git/atom/linux-user/m68k?h=spice_video_codecs 2022-09-27T07:30:09+00:00 2022-09-27T07:30:09+00:00 Ilya Leoshkevich 2022-09-06T00:08:35+00:00 urn:sha1:9f22020b91ae235be2b27c47d11e842872ec5e85 Provide MADV_* definitions using target_mman.h header, similar to what kernel does. Most architectures use the same values, with the exception of alpha and hppa. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220906000839.1672934-2-iii@linux.ibm.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu> 2022-06-28T04:43:22+00:00 Richard Henderson 2022-04-30T03:16:53+00:00 urn:sha1:a638af09b6c6b1259803a377a53ef242c5af6af5 While we had a call to do_m68k_semihosting in linux-user, it wasn't actually reachable. We don't include DISAS_INSN(halt) as an instruction unless system mode. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2022-06-02T07:35:02+00:00 Richard Henderson 2022-06-02T01:33:54+00:00 urn:sha1:aeeb90afcec3e18254bc6ac9c511f3b0a1a3796c Resolves: https://gitlab.com/qemu-project/qemu/-/issues/754 Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220602013401.303699-11-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu> 2022-06-02T07:35:02+00:00 Richard Henderson 2022-06-02T01:33:52+00:00 urn:sha1:8115fc9368e41f91a8bc27a78c2840beda989cb5 According to the M68040 Users Manual, section 8.4.3, Six word stack frame (format 2), Trace (and others) is supposed to record the next insn in PC and the address of the trapping instruction in ADDRESS. Create gen_raise_exception_format2 to record the trapping pc in env->mmu.ar. Update m68k_interrupt_all to pass the value to do_stack_frame. Update cpu_loop to handle EXCP_TRACE. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220602013401.303699-9-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu> 2022-06-02T07:35:02+00:00 Richard Henderson 2022-06-02T01:33:51+00:00 urn:sha1:710d747b2deaf5f5678aebb1fabbe00224e5cdde According to the M68040 Users Manual, section 8.4.3, Six word stack frame (format 2), Zero Div (and others) is supposed to record the next insn in PC and the address of the trapping instruction in ADDRESS. While the N, Z and V flags are documented to be undefine on DIV0, the C flag is documented as always cleared. Update helper_div* to take the instruction length as an argument and use raise_exception_format2. Hoist the reset of the C flag above the division by zero check. Update m68k_interrupt_all to pass mmu.ar to do_stack_frame. Update cpu_loop to pass mmu.ar to siginfo.si_addr, as the kernel does in trap_c(). Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220602013401.303699-8-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu> 2022-06-02T07:35:02+00:00 Richard Henderson 2022-06-02T01:33:50+00:00 urn:sha1:ad5a5cf97d80501be95f5d255d2ce133e0623b50 According to the M68040 Users Manual, section 8.4.3, Six word stack frame (format 2), CHK, CHK2 (and others) are supposed to record the next insn in PC and the address of the trapping instruction in ADDRESS. Create a raise_exception_format2 function to centralize recording of the trapping pc in mmu.ar, plus advancing to the next insn. Update m68k_interrupt_all to pass mmu.ar to do_stack_frame. Update cpu_loop to pass mmu.ar to siginfo.si_addr, as the kernel does in trap_c(). Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220602013401.303699-7-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu> 2022-06-02T07:35:02+00:00 Richard Henderson 2022-06-02T01:33:48+00:00 urn:sha1:cf213dacf8d9bc37889aeaebc781f5f55d705f0d These are raised by guest instructions, and should not fall through into the default abort case. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220602013401.303699-5-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu> 2022-06-02T07:35:02+00:00 Richard Henderson 2022-06-02T01:33:45+00:00 urn:sha1:79e1d527e13d35b976c947c48a70c23ef3586e76 Rather than adjust the PC in all of the consumers, raise the exception with the correct PC in the first place. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220602013401.303699-2-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu> 2022-04-06T12:31:55+00:00 Marc-André Lureau 2022-03-23T15:57:43+00:00 urn:sha1:0f9668e0c197ab6de95f61a906703a1d127c11f8 Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20220323155743.1585078-33-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> 2022-02-01T07:01:38+00:00 Serge Belyshev 2022-01-29T19:46:59+00:00 urn:sha1:b13e49bc86961c6725b2ebddd53898fe1366f6dc Signed-off-by: Serge Belyshev <belyshev@depni.sinp.msu.ru> Message-Id: <87ee4ql3yk.fsf_-_@depni.sinp.msu.ru> Signed-off-by: Laurent Vivier <laurent@vivier.eu>