Experimental fork of QEMU with video encoding patches https://git.openslx.org/bwlp/qemu.git/atom/linux-user/nios2?h=spice_video_codecs 2022-09-27T07:30:09+00:00 2022-09-27T07:30:09+00:00 Ilya Leoshkevich 2022-09-06T00:08:35+00:00 urn:sha1:9f22020b91ae235be2b27c47d11e842872ec5e85 Provide MADV_* definitions using target_mman.h header, similar to what kernel does. Most architectures use the same values, with the exception of alpha and hppa. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220906000839.1672934-2-iii@linux.ibm.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu> 2022-04-26T15:17:05+00:00 Richard Henderson 2022-04-21T15:17:29+00:00 urn:sha1:3747727aad1841bd07b7c9588b6d9b32182b1121 We missed out on a couple of exception types that may legitimately be raised by a userland program. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-59-richard.henderson@linaro.org> 2022-04-26T15:17:05+00:00 Richard Henderson 2022-04-21T15:17:28+00:00 urn:sha1:e84f1768449330a5b4c62a8aaa68f102ba6ec573 The exception return address for nios2 is the instruction after the one that was executing at the time of the exception. We have so far implemented this by advancing the pc during the process of raising the exception. It is perhaps a little less confusing to do this advance in the translator (and helpers) when raising the exception in the first place, so that we may more closely match kernel sources. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220421151735.31996-58-richard.henderson@linaro.org> 2022-04-26T15:17:05+00:00 Richard Henderson 2022-04-21T15:17:23+00:00 urn:sha1:410c6aaa3b44d5bdd1af7c1a465be7d5df2dfbf0 Indirect branches, plus eret and bret optionally raise an exception when branching to a misaligned address. The exception is required when an mmu is enabled, but enable it always because the fallback behaviour is not documented (though presumably it discards low bits). For the purposes of the linux-user cpu loop, if EXCP_UNALIGN (misaligned data) were to arrive, it would be treated the same as EXCP_UNALIGND (misaligned destination). See the !defined(CONFIG_NIOS2_ALIGNMENT_TRAP) block in kernel/traps.c. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-53-richard.henderson@linaro.org> 2022-04-26T15:16:41+00:00 Richard Henderson 2022-04-21T15:17:12+00:00 urn:sha1:345b7a8757e89a8f70a1fa09c6d51310650ef8be Division may (optionally) raise a division exception. Since the linux kernel has been prepared for this for some time, enable it by default. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-42-richard.henderson@linaro.org> 2022-04-26T15:16:41+00:00 Richard Henderson 2022-04-21T15:16:51+00:00 urn:sha1:dd4c6ee227202481d93b5329c5bd5d44ecb5c033 Drop the set of estatus in init_thread; it was clearly intended to be setting the value of CR_STATUS for the application, but we never actually performed that copy. However, the proper value is set in nios2_cpu_reset so we don't need to do anything here. We only initialize SP and EA in init_thread, there's no value in copying other uninitialized data into ENV. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-21-richard.henderson@linaro.org> 2022-04-26T15:16:41+00:00 Richard Henderson 2022-04-21T15:16:47+00:00 urn:sha1:17a406eec574e6e97fa7d5c70047026502a358cb It is cleaner to have a separate name for this variable. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-17-richard.henderson@linaro.org> 2022-04-26T15:16:40+00:00 Richard Henderson 2022-04-21T15:16:43+00:00 urn:sha1:3a0a43ec3c9c4c26f5a1a948e78311468e2930d6 Use the simpler signal interface, which forces us to supply the missing PC value to si_addr. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220421151735.31996-13-richard.henderson@linaro.org> 2022-04-26T15:16:40+00:00 Richard Henderson 2022-04-21T15:16:41+00:00 urn:sha1:fb4de9d2357bc42048a3ed3fcd15d8036e4c94a7 Since f5ef0e518d0, we have a real page mapped for kuser, which means the special casing for SIGSEGV can go away. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220421151735.31996-11-richard.henderson@linaro.org> 2022-04-26T15:16:40+00:00 Richard Henderson 2022-04-21T15:16:38+00:00 urn:sha1:1b5fb4d252c4403cbb893be6e38a26a119d054ef Drop the kernel-specific "pr2" code structure and use the qemu-specific error return value. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-8-richard.henderson@linaro.org>