bwlp/qemu.git/target-mips, branch spice_video_codecs

Move target-* CPU file into a target/ folder

2016-12-20T20:52:12+00:00

We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier [m68k part] Acked-by: Bastian Koppelmann [tricore part] Acked-by: Michael Walle [lm32 part] Acked-by: Cornelia Huck [s390x part] Reviewed-by: Christian Borntraeger [s390x part] Acked-by: Eduardo Habkost [i386 part] Acked-by: Artyom Tarasenko [sparc part] Acked-by: Richard Henderson [alpha part] Acked-by: Max Filippov [xtensa part] Reviewed-by: David Gibson [ppc part] Acked-by: Edgar E. Iglesias [crisµblaze part] Acked-by: Guan Xuetao [unicore32 part] Signed-off-by: Thomas Huth

target-mips: fix bad shifts in {dextp|dextpdp}

2016-12-04T00:57:06+00:00

Fixed issues in the MIPSDSP64 instructions dextp and dextpdp. Shifting can go out of 32 bit range. https://bugs.launchpad.net/qemu/+bug/1631625 Reported-by: Thomas Huth Reported-by: Jia Liu Signed-off-by: Yongbok Kim Reviewed-by: Thomas Huth

target-mips: Fix Loongson multimedia instructions.

2016-12-04T00:56:29+00:00

Needed to emit FPU exception on Loongson multimedia instructions executing if Status:CU1 is clear. or FPR changes may be missed on Linux. Signed-off-by: Heiher Signed-off-by: Fuxin Zhang Reviewed-by: Yongbok Kim Signed-off-by: Yongbok Kim

target-mips: Fix Loongson multimedia 'or' instruction.

2016-12-02T16:11:09+00:00

Signed-off-by: Heiher Signed-off-by: Fuxin Zhang Reviewed-by: Yongbok Kim Signed-off-by: Yongbok Kim

target-mips: Fix Loongson pandn instruction.

2016-12-02T16:11:08+00:00

pandn FD, FS, FT Operation: FD = ((NOT FS) AND FT) Signed-off-by: Heiher Signed-off-by: Fuxin Zhang Reviewed-by: Yongbok Kim Signed-off-by: Yongbok Kim

log: Add locking to large logging blocks

2016-11-01T16:29:03+00:00

Reuse the existing locking provided by stdio to keep in_asm, cpu, op, op_opt, op_ind, and out_asm as contiguous blocks. While it isn't possible to interleave e.g. in_asm or op_opt logs because of the TB lock protecting all code generation, it is possible to interleave cpu logs, or to interleave a cpu dump with an out_asm dump. For mingw32, we appear to have no viable solution for this. The locking functions are not properly exported from the system runtime library. Reviewed-by: Paolo Bonzini Signed-off-by: Richard Henderson

clean-up: removed duplicate #includes

2016-10-28T15:17:24+00:00

Some files contain multiple #includes of the same header file. Removed most of those unnecessary duplicate entries using scripts/clean-includes. Reviewed-by: Thomas Huth Signed-off-by: Anand J Signed-off-by: Michael Tokarev

exec: move cpu_exec_init() calls to realize functions

2016-10-24T19:29:16+00:00

Modify all CPUs to call it from XXX_cpu_realizefn() function. Remove all the cannot_destroy_with_object_finalize_yet as unsafe references have been moved to cpu_exec_realizefn(). (tested with QOM command provided by commit 4c315c27) for arm: Setting of cpu->mp_affinity is moved from arm_cpu_initfn() to arm_cpu_realizefn() as setting of cpu_index is now done in cpu_exec_realizefn(). To avoid to overwrite an user defined value, we set it to an invalid value by default, and update it in realize function only if the value is still invalid. Signed-off-by: Laurent Vivier Reviewed-by: David Gibson Reviewed-by: Igor Mammedov Reviewed-by: Eduardo Habkost Reviewed-by: Andrew Jones Signed-off-by: Eduardo Habkost

target-mips: generate fences

2016-09-23T06:07:30+00:00

Make use of memory barrier TCG opcode in MIPS front end. Signed-off-by: Leon Alrae Reviewed-by: Richard Henderson

target-mips: add 24KEc CPU definition

2016-09-23T06:07:29+00:00

Define a new CPU definition supporting 24KEc cores, similar to the existing 24Kc, but with added support for DSP instructions and MIPS16e (and without FPU). Signed-off-by: André Draszik Signed-off-by: Leon Alrae