Experimental fork of QEMU with video encoding patches https://git.openslx.org/bwlp/qemu.git/atom/target-sparc?h=spice_video_codecs 2016-12-20T20:52:12+00:00 2016-12-20T20:52:12+00:00 Thomas Huth 2016-10-11T06:56:52+00:00 urn:sha1:fcf5ef2ab52c621a4617ebbef36bf43b4003f4c0 We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com> 2016-11-01T16:29:03+00:00 Richard Henderson 2016-09-22T22:17:10+00:00 urn:sha1:1ee73216f4ccd2f3b6eb818feb165b3cf5a1944c Reuse the existing locking provided by stdio to keep in_asm, cpu, op, op_opt, op_ind, and out_asm as contiguous blocks. While it isn't possible to interleave e.g. in_asm or op_opt logs because of the TB lock protecting all code generation, it is possible to interleave cpu logs, or to interleave a cpu dump with an out_asm dump. For mingw32, we appear to have no viable solution for this. The locking functions are not properly exported from the system runtime library. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net> 2016-11-01T11:21:02+00:00 Peter Maydell 2016-11-01T11:21:02+00:00 urn:sha1:bf99fd3983d7185178a0f65ce29bb94b1aecaed1 target-sparc updates for atomics and alignment # gpg: Signature made Mon 31 Oct 2016 20:47:57 GMT # gpg: using RSA key 0xAD1270CC4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" # Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B * remotes/rth/tags/pull-sparc-20161031-2: target-sparc: Use tcg_gen_atomic_cmpxchg_tl target-sparc: Use tcg_gen_atomic_xchg_tl target-sparc: Remove MMU_MODE*_SUFFIX target-sparc: Allow 4-byte alignment on fp mem ops target-sparc: Implement ldqf and stqf inline target-sparc: Remove asi helper code handled inline target-sparc: Implement BCOPY/BFILL inline target-sparc: Implement cas_asi/casx_asi inline target-sparc: Implement ldstub_asi inline target-sparc: Implement swap_asi inline target-sparc: Handle more twinx asis target-sparc: Use MMU_PHYS_IDX for bypass asis target-sparc: Add MMU_PHYS_IDX target-sparc: Introduce cpu_raise_exception_ra target-sparc: Use overalignment flags for twinx and block asis Signed-off-by: Peter Maydell <peter.maydell@linaro.org> 2016-10-31T20:46:48+00:00 Richard Henderson 2016-09-13T02:11:18+00:00 urn:sha1:5a7267b6a9e94c264ca77a7ca5a239e70dac81da Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net> 2016-10-31T20:46:48+00:00 Richard Henderson 2016-09-13T02:01:53+00:00 urn:sha1:da1bcae65288bdd51e0a7203d1e6c9cde1be5b3d Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net> 2016-10-31T20:46:48+00:00 Richard Henderson 2016-07-14T20:21:11+00:00 urn:sha1:47b2696b975b794c6fa7b9fa8ae4699e749d662c The functions that these generate are no longer used. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net> 2016-10-31T20:46:47+00:00 Richard Henderson 2016-08-31T17:48:03+00:00 urn:sha1:cb21b4da6cca1bb4e3f5fefb698fb9e4d00c8f66 The cpu is allowed to require stricter alignment on these 8- and 16-byte operations, and the OS is required to fix up the accesses as necessary, so the previous code was not wrong. However, we can easily handle this misalignment for all direct 8-byte operations and for direct 16-byte loads. We must retain 16-byte alignment for 16-byte stores, so that we don't have to probe for writability of a second page before performing the first of two 8-byte stores. We also retain 8-byte alignment for no-fault loads, since they are rare and it's not worth extending the helpers for this. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net> 2016-10-31T20:46:47+00:00 Richard Henderson 2016-07-14T18:47:08+00:00 urn:sha1:f939ffe5a022a8798824e2720ed5a14186fca6b6 At the same time, fix a problem with stqf_asi, when a write might access two pages. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net> 2016-10-31T20:46:47+00:00 Richard Henderson 2016-07-12T22:09:54+00:00 urn:sha1:918d9a2c9d36378a3cf6636018900a4731c83b9d Now that we never call out to helpers when direct accesses can handle an asi, remove the corresponding code in those helpers. For ldda, this removes the entire helper. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net> 2016-10-31T20:46:47+00:00 Richard Henderson 2016-07-14T19:46:19+00:00 urn:sha1:34810610acbde7a0745be3a88e99f2ef9282260f Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>