<feed xmlns='http://www.w3.org/2005/Atom'>
<title>bwlp/qemu.git/target/avr, branch spice_video_codecs</title>
<subtitle>Experimental fork of QEMU with video encoding patches</subtitle>
<id>https://git.openslx.org/bwlp/qemu.git/atom/target/avr?h=spice_video_codecs</id>
<link rel='self' href='https://git.openslx.org/bwlp/qemu.git/atom/target/avr?h=spice_video_codecs'/>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/'/>
<updated>2022-10-26T01:11:28+00:00</updated>
<entry>
<title>target/avr: Convert to tcg_ops restore_state_to_opc</title>
<updated>2022-10-26T01:11:28+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-10-24T10:05:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=f06c1ad4c62b8c91608c36cd3c870524979a278e'/>
<id>urn:sha1:f06c1ad4c62b8c91608c36cd3c870524979a278e</id>
<content type='text'>
Reviewed-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>accel/tcg: Introduce tb_pc and log_pc</title>
<updated>2022-10-04T19:13:12+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-08-15T20:16:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=fbf59aad178d98afe193fa872a2d880266a75269'/>
<id>urn:sha1:fbf59aad178d98afe193fa872a2d880266a75269</id>
<content type='text'>
The availability of tb-&gt;pc will shortly be conditional.
Introduce accessor functions to minimize ifdefs.

Pass around a known pc to places like tcg_gen_code,
where the caller must already have the value.

Reviewed-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>hw/core: Add CPUClass.get_pc</title>
<updated>2022-10-04T19:13:12+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-09-30T17:31:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=e4fdf9df5b1c2aa427de796bea973520027ddd15'/>
<id>urn:sha1:e4fdf9df5b1c2aa427de796bea973520027ddd15</id>
<content type='text'>
Populate this new method for all targets.  Always match
the result that would be given by cpu_get_tb_cpu_state,
as we will want these values to correspond in the logs.

Reviewed-by: Taylor Simpson &lt;tsimpson@quicinc.com&gt;
Reviewed-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Reviewed-by: Mark Cave-Ayland &lt;mark.cave-ayland@ilande.co.uk&gt; (target/sparc)
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
---
Cc: Eduardo Habkost &lt;eduardo@habkost.net&gt; (supporter:Machine core)
Cc: Marcel Apfelbaum &lt;marcel.apfelbaum@gmail.com&gt; (supporter:Machine core)
Cc: "Philippe Mathieu-Daudé" &lt;f4bug@amsat.org&gt; (reviewer:Machine core)
Cc: Yanan Wang &lt;wangyanan55@huawei.com&gt; (reviewer:Machine core)
Cc: Michael Rolnik &lt;mrolnik@gmail.com&gt; (maintainer:AVR TCG CPUs)
Cc: "Edgar E. Iglesias" &lt;edgar.iglesias@gmail.com&gt; (maintainer:CRIS TCG CPUs)
Cc: Taylor Simpson &lt;tsimpson@quicinc.com&gt; (supporter:Hexagon TCG CPUs)
Cc: Song Gao &lt;gaosong@loongson.cn&gt; (maintainer:LoongArch TCG CPUs)
Cc: Xiaojuan Yang &lt;yangxiaojuan@loongson.cn&gt; (maintainer:LoongArch TCG CPUs)
Cc: Laurent Vivier &lt;laurent@vivier.eu&gt; (maintainer:M68K TCG CPUs)
Cc: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt; (reviewer:MIPS TCG CPUs)
Cc: Aleksandar Rikalo &lt;aleksandar.rikalo@syrmia.com&gt; (reviewer:MIPS TCG CPUs)
Cc: Chris Wulff &lt;crwulff@gmail.com&gt; (maintainer:NiosII TCG CPUs)
Cc: Marek Vasut &lt;marex@denx.de&gt; (maintainer:NiosII TCG CPUs)
Cc: Stafford Horne &lt;shorne@gmail.com&gt; (odd fixer:OpenRISC TCG CPUs)
Cc: Yoshinori Sato &lt;ysato@users.sourceforge.jp&gt; (reviewer:RENESAS RX CPUs)
Cc: Mark Cave-Ayland &lt;mark.cave-ayland@ilande.co.uk&gt; (maintainer:SPARC TCG CPUs)
Cc: Bastian Koppelmann &lt;kbastian@mail.uni-paderborn.de&gt; (maintainer:TriCore TCG CPUs)
Cc: Max Filippov &lt;jcmvbkbc@gmail.com&gt; (maintainer:Xtensa TCG CPUs)
Cc: qemu-arm@nongnu.org (open list:ARM TCG CPUs)
Cc: qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs)
Cc: qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs)
Cc: qemu-s390x@nongnu.org (open list:S390 TCG CPUs)
</content>
</entry>
<entry>
<title>accel/tcg: Add pc and host_pc params to gen_intermediate_code</title>
<updated>2022-09-06T07:04:26+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-08-11T20:48:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=306c872103b4d0986c9f671eb7538b0b70bf69b5'/>
<id>urn:sha1:306c872103b4d0986c9f671eb7538b0b70bf69b5</id>
<content type='text'>
Pass these along to translator_loop -- pc may be used instead
of tb-&gt;pc, and host_pc is currently unused.  Adjust all targets
at one time.

Acked-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
Acked-by: Ilya Leoshkevich &lt;iii@linux.ibm.com&gt;
Tested-by: Ilya Leoshkevich &lt;iii@linux.ibm.com&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>target/avr: Disable interrupts when env-&gt;skip set</title>
<updated>2022-09-01T05:42:21+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-08-26T20:53:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=36027c70974fef1392e6c73dfb94c3f94f0930bc'/>
<id>urn:sha1:36027c70974fef1392e6c73dfb94c3f94f0930bc</id>
<content type='text'>
This bit is not saved across interrupts, so we must
delay delivering the interrupt until the skip has
been processed.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1118
Reviewed-by: Michael Rolnik &lt;mrolnik@gmail.com&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>target/avr: Only execute one interrupt at a time</title>
<updated>2022-09-01T05:41:57+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-08-26T20:35:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=cecaad540155927f2faf1b6897c72cc59074cb45'/>
<id>urn:sha1:cecaad540155927f2faf1b6897c72cc59074cb45</id>
<content type='text'>
We cannot deliver two interrupts simultaneously;
the first interrupt handler must execute first.

Reviewed-by: Michael Rolnik &lt;mrolnik@gmail.com&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>target/avr: Call avr_cpu_do_interrupt directly</title>
<updated>2022-09-01T05:41:16+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-08-26T20:32:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=9e1b2375daabc4d133baf08766676c5d301bade5'/>
<id>urn:sha1:9e1b2375daabc4d133baf08766676c5d301bade5</id>
<content type='text'>
There is no need to go through cc-&gt;tcg_ops when
we know what value that must have.

Reviewed-by: Michael Rolnik &lt;mrolnik@gmail.com&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>target/avr: Support probe argument to tlb_fill</title>
<updated>2022-09-01T05:39:47+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-08-23T04:57:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=7bccb9e3222024470073568d05c2121386564ca3'/>
<id>urn:sha1:7bccb9e3222024470073568d05c2121386564ca3</id>
<content type='text'>
While there are no target-specific nonfaulting probes,
generic code may grow some uses at some point.

Note that the attrs argument was incorrect -- it should have
been MEMTXATTRS_UNSPECIFIED. Just use the simpler interface.

Reviewed-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>target/avr: Drop avr_cpu_memory_rw_debug()</title>
<updated>2022-06-20T20:11:36+00:00</updated>
<author>
<name>Bin Meng</name>
</author>
<published>2022-03-22T09:50:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=adb5974dcc5ee7fe122c74fb85d3bae331101ec3'/>
<id>urn:sha1:adb5974dcc5ee7fe122c74fb85d3bae331101ec3</id>
<content type='text'>
CPUClass::memory_rw_debug() holds a callback for GDB memory access.
If not provided, cpu_memory_rw_debug() is used by the GDB stub.
Drop avr_cpu_memory_rw_debug() which does nothing special.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Message-Id: &lt;20220322095004.70682-1-bmeng.cn@gmail.com&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>Clean up decorations and whitespace around header guards</title>
<updated>2022-05-11T14:50:32+00:00</updated>
<author>
<name>Markus Armbruster</name>
</author>
<published>2022-05-06T13:49:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=ea9cea93c69d508a333dd1b0cb1a44f6daf80b63'/>
<id>urn:sha1:ea9cea93c69d508a333dd1b0cb1a44f6daf80b63</id>
<content type='text'>
Cleaned up with scripts/clean-header-guards.pl.

Signed-off-by: Markus Armbruster &lt;armbru@redhat.com&gt;
Message-Id: &lt;20220506134911.2856099-5-armbru@redhat.com&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
</feed>
