<feed xmlns='http://www.w3.org/2005/Atom'>
<title>bwlp/qemu.git/target/cris, branch spice_video_codecs</title>
<subtitle>Experimental fork of QEMU with video encoding patches</subtitle>
<id>https://git.openslx.org/bwlp/qemu.git/atom/target/cris?h=spice_video_codecs</id>
<link rel='self' href='https://git.openslx.org/bwlp/qemu.git/atom/target/cris?h=spice_video_codecs'/>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/'/>
<updated>2022-10-31T21:31:41+00:00</updated>
<entry>
<title>accel/tcg: Remove will_exit argument from cpu_restore_state</title>
<updated>2022-10-31T21:31:41+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-10-24T13:09:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=3d419a4dd227f174447e0b3978028a1cd52ccc5e'/>
<id>urn:sha1:3d419a4dd227f174447e0b3978028a1cd52ccc5e</id>
<content type='text'>
The value passed is always true, and if the target's
synchronize_from_tb hook is non-trivial, not exiting
may be erroneous.

Reviewed-by: Claudio Fontana &lt;cfontana@suse.de&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>target/cris: Convert to tcg_ops restore_state_to_opc</title>
<updated>2022-10-26T01:11:28+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-10-24T10:08:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=4060474284cd6c7012c50dda743c6c151b92be87'/>
<id>urn:sha1:4060474284cd6c7012c50dda743c6c151b92be87</id>
<content type='text'>
Reviewed-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>hw/core: Add CPUClass.get_pc</title>
<updated>2022-10-04T19:13:12+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-09-30T17:31:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=e4fdf9df5b1c2aa427de796bea973520027ddd15'/>
<id>urn:sha1:e4fdf9df5b1c2aa427de796bea973520027ddd15</id>
<content type='text'>
Populate this new method for all targets.  Always match
the result that would be given by cpu_get_tb_cpu_state,
as we will want these values to correspond in the logs.

Reviewed-by: Taylor Simpson &lt;tsimpson@quicinc.com&gt;
Reviewed-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Reviewed-by: Mark Cave-Ayland &lt;mark.cave-ayland@ilande.co.uk&gt; (target/sparc)
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
---
Cc: Eduardo Habkost &lt;eduardo@habkost.net&gt; (supporter:Machine core)
Cc: Marcel Apfelbaum &lt;marcel.apfelbaum@gmail.com&gt; (supporter:Machine core)
Cc: "Philippe Mathieu-Daudé" &lt;f4bug@amsat.org&gt; (reviewer:Machine core)
Cc: Yanan Wang &lt;wangyanan55@huawei.com&gt; (reviewer:Machine core)
Cc: Michael Rolnik &lt;mrolnik@gmail.com&gt; (maintainer:AVR TCG CPUs)
Cc: "Edgar E. Iglesias" &lt;edgar.iglesias@gmail.com&gt; (maintainer:CRIS TCG CPUs)
Cc: Taylor Simpson &lt;tsimpson@quicinc.com&gt; (supporter:Hexagon TCG CPUs)
Cc: Song Gao &lt;gaosong@loongson.cn&gt; (maintainer:LoongArch TCG CPUs)
Cc: Xiaojuan Yang &lt;yangxiaojuan@loongson.cn&gt; (maintainer:LoongArch TCG CPUs)
Cc: Laurent Vivier &lt;laurent@vivier.eu&gt; (maintainer:M68K TCG CPUs)
Cc: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt; (reviewer:MIPS TCG CPUs)
Cc: Aleksandar Rikalo &lt;aleksandar.rikalo@syrmia.com&gt; (reviewer:MIPS TCG CPUs)
Cc: Chris Wulff &lt;crwulff@gmail.com&gt; (maintainer:NiosII TCG CPUs)
Cc: Marek Vasut &lt;marex@denx.de&gt; (maintainer:NiosII TCG CPUs)
Cc: Stafford Horne &lt;shorne@gmail.com&gt; (odd fixer:OpenRISC TCG CPUs)
Cc: Yoshinori Sato &lt;ysato@users.sourceforge.jp&gt; (reviewer:RENESAS RX CPUs)
Cc: Mark Cave-Ayland &lt;mark.cave-ayland@ilande.co.uk&gt; (maintainer:SPARC TCG CPUs)
Cc: Bastian Koppelmann &lt;kbastian@mail.uni-paderborn.de&gt; (maintainer:TriCore TCG CPUs)
Cc: Max Filippov &lt;jcmvbkbc@gmail.com&gt; (maintainer:Xtensa TCG CPUs)
Cc: qemu-arm@nongnu.org (open list:ARM TCG CPUs)
Cc: qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs)
Cc: qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs)
Cc: qemu-s390x@nongnu.org (open list:S390 TCG CPUs)
</content>
</entry>
<entry>
<title>accel/tcg: Add pc and host_pc params to gen_intermediate_code</title>
<updated>2022-09-06T07:04:26+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-08-11T20:48:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=306c872103b4d0986c9f671eb7538b0b70bf69b5'/>
<id>urn:sha1:306c872103b4d0986c9f671eb7538b0b70bf69b5</id>
<content type='text'>
Pass these along to translator_loop -- pc may be used instead
of tb-&gt;pc, and host_pc is currently unused.  Adjust all targets
at one time.

Acked-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
Acked-by: Ilya Leoshkevich &lt;iii@linux.ibm.com&gt;
Tested-by: Ilya Leoshkevich &lt;iii@linux.ibm.com&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>Normalize header guard symbol definition</title>
<updated>2022-05-11T14:50:26+00:00</updated>
<author>
<name>Markus Armbruster</name>
</author>
<published>2022-05-06T13:49:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=4f31b54bfe52c72be9c17c158b38924e6cefcd0f'/>
<id>urn:sha1:4f31b54bfe52c72be9c17c158b38924e6cefcd0f</id>
<content type='text'>
We commonly define the header guard symbol without an explicit value.
Normalize the exceptions.

Done with scripts/clean-header-guards.pl.

Signed-off-by: Markus Armbruster &lt;armbru@redhat.com&gt;
Message-Id: &lt;20220506134911.2856099-4-armbru@redhat.com&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>exec/translator: Pass the locked filepointer to disas_log hook</title>
<updated>2022-04-20T17:51:11+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-04-17T18:29:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=8eb806a763f4a804ac80a6d4f4679c60fd66d8fa'/>
<id>urn:sha1:8eb806a763f4a804ac80a6d4f4679c60fd66d8fa</id>
<content type='text'>
We have fetched and locked the logfile in translator_loop.
Pass the filepointer down to the disas_log hook so that it
need not be fetched and locked again.

Reviewed-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-Id: &lt;20220417183019.755276-13-richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>target: Use ArchCPU as interface to target CPU</title>
<updated>2022-03-06T21:23:09+00:00</updated>
<author>
<name>Philippe Mathieu-Daudé</name>
</author>
<published>2022-02-14T16:15:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=b36e239e08a031025e52c4191198ee8381e2e6de'/>
<id>urn:sha1:b36e239e08a031025e52c4191198ee8381e2e6de</id>
<content type='text'>
ArchCPU is our interface with target-specific code. Use it as
a forward-declared opaque pointer (abstract type), having its
structure defined by each target.

Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Signed-off-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Message-Id: &lt;20220214183144.27402-15-f4bug@amsat.org&gt;
</content>
</entry>
<entry>
<title>target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro</title>
<updated>2022-03-06T21:23:09+00:00</updated>
<author>
<name>Philippe Mathieu-Daudé</name>
</author>
<published>2022-02-14T16:08:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=9295b1aa92d3efb3c08b71ee751fbfd83ea02f4d'/>
<id>urn:sha1:9295b1aa92d3efb3c08b71ee751fbfd83ea02f4d</id>
<content type='text'>
Replace the boilerplate code to declare CPU QOM types
and macros, and forward-declare the CPU instance type.

Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Signed-off-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Message-Id: &lt;20220214183144.27402-14-f4bug@amsat.org&gt;
</content>
</entry>
<entry>
<title>target: Use CPUArchState as interface to target-specific CPU state</title>
<updated>2022-03-06T21:23:09+00:00</updated>
<author>
<name>Philippe Mathieu-Daudé</name>
</author>
<published>2022-02-07T12:35:58+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=1ea4a06af0f6578e5d0ddcea148503290b1c4907'/>
<id>urn:sha1:1ea4a06af0f6578e5d0ddcea148503290b1c4907</id>
<content type='text'>
While CPUState is our interface with generic code, CPUArchState is
our interface with target-specific code. Use CPUArchState as an
abstract type, defined by each target.

Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Signed-off-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Message-Id: &lt;20220214183144.27402-13-f4bug@amsat.org&gt;
</content>
</entry>
<entry>
<title>exec/exec-all: Move 'qemu/log.h' include in units requiring it</title>
<updated>2022-02-21T09:18:06+00:00</updated>
<author>
<name>Philippe Mathieu-Daudé</name>
</author>
<published>2022-02-07T08:27:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=cd6174843b0896c9e57176159b38ecba45bade0e'/>
<id>urn:sha1:cd6174843b0896c9e57176159b38ecba45bade0e</id>
<content type='text'>
Many files use "qemu/log.h" declarations but neglect to include
it (they inherit it via "exec/exec-all.h"). "exec/exec-all.h" is
a core component and shouldn't be used that way. Move the
"qemu/log.h" inclusion locally to each unit requiring it.

Signed-off-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Acked-by: Thomas Huth &lt;thuth@redhat.com&gt;
Message-Id: &lt;20220207082756.82600-10-f4bug@amsat.org&gt;
Signed-off-by: Thomas Huth &lt;thuth@redhat.com&gt;
</content>
</entry>
</feed>
