bwlp/qemu.git/target/hexagon/mmvec, branch master Experimental fork of QEMU with video encoding patches https://git.openslx.org/bwlp/qemu.git/atom/target/hexagon/mmvec?h=master 2022-03-12T17:14:22+00:00 target/hexagon: remove unused variable 2022-03-12T17:14:22+00:00 Zongyuan Li 2022-01-24T06:43:39+00:00 urn:sha1:4a818b3767220dcd21cf5cc7f12e33e28c2073ed When building with clang version 13.0.0 (eg. Fedora 13.0.0-3.fc35), two unused variables introduced by macro GATHER_FUNCTION and SCATTER_FUNCTION will cause building process failure due to [-Werror -Wunused-variable]. Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/831 Message-Id: <20220124064339.56027-1-zongyuan.li@smartx.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Hexagon HVX (target/hexagon) instruction decoding 2021-11-03T21:01:36+00:00 Taylor Simpson 2021-02-07T18:42:57+00:00 urn:sha1:60d1180b68944c3dbaad8239e60515e4c5c4b00f Add new file to target/hexagon/meson.build Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Hexagon HVX (target/hexagon) instruction utility functions 2021-11-03T21:01:30+00:00 Taylor Simpson 2021-03-11T01:38:45+00:00 urn:sha1:82f8b3dce2918813ed5807ec8f1e94c5b2300f6c Functions to support scatter/gather Add new file to target/hexagon/meson.build Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Hexagon HVX (target/hexagon) macros 2021-11-03T21:01:28+00:00 Taylor Simpson 2021-03-07T23:30:59+00:00 urn:sha1:64458f4855302373229eb7ca1902b65a7578ab7d macros to interface with the generator macros referenced in instruction semantics Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Hexagon HVX (target/hexagon) add Hexagon Vector eXtensions (HVX) to core 2021-11-03T21:01:26+00:00 Taylor Simpson 2021-03-17T16:48:57+00:00 urn:sha1:a1559537d183bf1f4e2cfef972610c8c9e1a6aa5 HVX is a set of wide vector instructions. Machine state includes vector registers (VRegs) vector predicate registers (QRegs) temporary registers for intermediate values store buffer (masked stores and scatter/gather) Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>