Experimental fork of QEMU with video encoding patches https://git.openslx.org/bwlp/qemu.git/atom/target/hppa/helper.h?h=spice_video_codecs 2022-02-28T18:04:06+00:00 2022-02-28T18:04:06+00:00 Richard Henderson 2022-02-17T01:06:22+00:00 urn:sha1:8929906e212cbe606e361cbd32917dcbe5bb6dd0 The dh_alias redirect is intended to handle TCG types as distinguished from C types. TCG does not distinguish signed int from unsigned int, because they are the same size. However, we need to retain this distinction for dh_typecode, lest we fail to extend abi types properly for the host call parameters. This bug was detected when running the 'arm' emulator on an s390 system. The s390 uses TCG_TARGET_EXTEND_ARGS which triggers code in tcg_gen_callN to extend 32 bit values to 64 bits; the incorrect sign data in the typemask for each argument caused the values to be extended as unsigned values. This simple program exhibits the problem: static volatile int num = -9; static volatile int den = -5; int main(void) { int quo = num / den; printf("num %d den %d quo %d\n", num, den, quo); exit(0); } When run on the broken qemu, this results in: num -9 den -5 quo 0 The correct result is: num -9 den -5 quo 1 Fixes: 7319d83a735 ("tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/876 Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reported-by: Christian Ehrhardt <christian.ehrhardt@canonical.com> Tested-by: Christian Ehrhardt <christian.ehrhardt@canonical.com> Tested-by: Keith Packard <keithp@keithp.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2022-02-02T17:46:42+00:00 Helge Deller 2022-01-05T22:09:04+00:00 urn:sha1:4a4554c6c561971197dffc80d641dc17ee2314dd Almost all PA-RISC machines have either a button that is labeled with 'TOC' or a BMC/GSP function to trigger a TOC. TOC is a non-maskable interrupt that is sent to the processor. This can be used for diagnostic purposes like obtaining a stack trace/register dump or to enter KDB/KGDB in Linux. This patch adds support for such an emulated TOC button. It wires up the qemu monitor "nmi" command to trigger a TOC. For that it provides the hppa_nmi function which is assigned to the nmi_monitor_handler function pointer. When called it raises the EXCP_TOC hardware interrupt in the hppa_cpu_do_interrupt() function. The interrupt function then calls the architecturally defined TOC function in SeaBIOS-hppa firmware (at fixed address 0xf0000000). According to the PA-RISC PDC specification, the SeaBIOS firmware then writes the CPU registers into PIM (processor internal memmory) for later analysis. In order to write all registers it needs to know the contents of the CPU "shadow registers" and the IASQ- and IAOQ-back values. The IAOQ/IASQ values are provided by qemu in shadow registers when entering the SeaBIOS TOC function. This patch adds a new aritificial opcode "getshadowregs" (0xfffdead2) which restores the original values of the shadow registers. With this opcode SeaBIOS can store those registers as well into PIM before calling an OS-provided TOC handler. To trigger a TOC, switch to the qemu monitor with Ctrl-A C, and type in the command "nmi". After the TOC started the OS-debugger, exit the qemu monitor with Ctrl-A C. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> 2021-06-19T15:51:11+00:00 Richard Henderson 2021-03-18T16:01:01+00:00 urn:sha1:7319d83a735004ba24b439491a9d7727dac2ddbe We will shortly be interested in distinguishing pointers from integers in the helper's declaration, as well as a true void return. We currently have two parallel 1 bit fields; merge them and expand to a 3 bit field. Our current maximum is 7 helper arguments, plus the return makes 8 * 3 = 24 bits used within the uint32_t typemask. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2020-01-27T18:49:51+00:00 Richard Henderson 2020-01-17T01:46:38+00:00 urn:sha1:b1af755c33bf0d690553a5ccd93689dfd15a98e8 The PA-RISC 1.1 specification says that LDCW must be aligned mod 16 or the operation is undefined. However, real hardware only generates an unaligned access trap for unaligned mod 4. Match real hardware, but diagnose with GUEST_ERROR a violation of the specification. At the same time fix a bug in the initialization of mop, where the size was specified twice, and another to free the zero temporary. Tested-by: Helge Deller <deller@gmx.de> Reported-by: Helge Deller <deller@gmx.de> Suggested-by: John David Anglin <dave.anglin@bell.net> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2019-03-12T16:13:43+00:00 Sven Schnelle 2019-03-11T19:16:00+00:00 urn:sha1:d5de20bd84ae3a6f6c194f0088cfcb4d4f6af602 Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-10-svens@stackframe.org> [rth: Add required tlb flushing when prot id registers change.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2018-01-31T13:30:50+00:00 Richard Henderson 2018-01-24T23:03:25+00:00 urn:sha1:eed142195c95a6c50545fa7a28e725d780ab9636 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2018-01-31T13:30:49+00:00 Helge Deller 2017-12-29T06:04:57+00:00 urn:sha1:6210db057a6f255f8d5caff1507f14185526df7a Real hardware would use an external device to control the power. But for the moment let's invent instructions in reserved space, to be used by our custom firmware. Signed-off-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2018-01-30T18:22:26+00:00 Richard Henderson 2017-11-05T09:50:47+00:00 urn:sha1:2dfcca9ffc0131f0d740dea27ebff04be01f871b Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2018-01-30T18:22:26+00:00 Richard Henderson 2017-10-27T16:33:23+00:00 urn:sha1:63300a00ab52c770f8a76218d4a3a75e0db8a6d0 We now have all of the TLB manipulation instructions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2018-01-30T18:22:26+00:00 Richard Henderson 2017-10-27T14:26:36+00:00 urn:sha1:8d6ae7fb3a9c4369979bcc7188966fa725eed033 The TLB can now be populated, but it cannot yet be cleared. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>