<feed xmlns='http://www.w3.org/2005/Atom'>
<title>bwlp/qemu.git/target/microblaze/helper.h, branch spice_video_codecs</title>
<subtitle>Experimental fork of QEMU with video encoding patches</subtitle>
<id>https://git.openslx.org/bwlp/qemu.git/atom/target/microblaze/helper.h?h=spice_video_codecs</id>
<link rel='self' href='https://git.openslx.org/bwlp/qemu.git/atom/target/microblaze/helper.h?h=spice_video_codecs'/>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/'/>
<updated>2020-09-01T14:43:35+00:00</updated>
<entry>
<title>target/microblaze: Add flags markup to some helpers</title>
<updated>2020-09-01T14:43:35+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2020-08-25T14:40:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=e269b4bdf228f57f6671b7692c08f7304179a4c4'/>
<id>urn:sha1:e269b4bdf228f57f6671b7692c08f7304179a4c4</id>
<content type='text'>
The mmu_read, mmu_write, get, and put helpers do not touch the
general registers, or any of the other variables managed by tcg.

Tested-by: Edgar E. Iglesias &lt;edgar.iglesias@xilinx.com&gt;
Reviewed-by: Edgar E. Iglesias &lt;edgar.iglesias@xilinx.com&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>target/microblaze: Use cc-&gt;do_unaligned_access</title>
<updated>2020-09-01T14:43:35+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2020-08-21T03:29:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=ab0c8d0f5b3377eba2c14116e199573583ea0089'/>
<id>urn:sha1:ab0c8d0f5b3377eba2c14116e199573583ea0089</id>
<content type='text'>
This fixes the problem in which unaligned stores succeeded,
but then we raised the exception after modifying memory.
Store the ESS for the unaligned data access in the iflags
for the insn, so that it can be found during unwind.

Tested-by: Edgar E. Iglesias &lt;edgar.iglesias@xilinx.com&gt;
Reviewed-by: Edgar E. Iglesias &lt;edgar.iglesias@xilinx.com&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>target/microblaze: Fix cpu unwind for stackprot</title>
<updated>2020-09-01T14:41:38+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2020-08-25T14:45:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=3f203194550108a72e8ee55d1b8bcb2333222b71'/>
<id>urn:sha1:3f203194550108a72e8ee55d1b8bcb2333222b71</id>
<content type='text'>
Restore the correct PC when an exception must be raised.

Tested-by: Edgar E. Iglesias &lt;edgar.iglesias@xilinx.com&gt;
Reviewed-by: Edgar E. Iglesias &lt;edgar.iglesias@xilinx.com&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>target/microblaze: Mark fpu helpers TCG_CALL_NO_WG</title>
<updated>2020-09-01T14:41:38+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2020-08-24T15:57:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=3986c650a25e645a2b39795e5004d7e0e1c7b8b1'/>
<id>urn:sha1:3986c650a25e645a2b39795e5004d7e0e1c7b8b1</id>
<content type='text'>
Now that FSR is no longer a tcg global temp, we can say that
the fpu helpers do not write to tcg temps.  All temps are
read implicitly by the fpu exception path.

Tested-by: Edgar E. Iglesias &lt;edgar.iglesias@xilinx.com&gt;
Reviewed-by: Edgar E. Iglesias &lt;edgar.iglesias@xilinx.com&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>target/microblaze: Unwind properly when raising divide-by-zero</title>
<updated>2020-09-01T14:41:38+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2020-08-18T06:12:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=e98651d9ca475259a6721f6f1cff5da1ad4f0cc1'/>
<id>urn:sha1:e98651d9ca475259a6721f6f1cff5da1ad4f0cc1</id>
<content type='text'>
Restore the correct pc when raising divide-by-zero.  Also, the
MSR[DZO] bit is sticky -- it is not cleared with a successful divide.

Tested-by: Edgar E. Iglesias &lt;edgar.iglesias@xilinx.com&gt;
Reviewed-by: Edgar E. Iglesias &lt;edgar.iglesias@xilinx.com&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>target/microblaze: Implement cmp and cmpu inline</title>
<updated>2020-09-01T14:41:38+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2020-08-25T14:31:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=58b48b637db61e28a5e6c1ec9fce42b9f79c7b36'/>
<id>urn:sha1:58b48b637db61e28a5e6c1ec9fce42b9f79c7b36</id>
<content type='text'>
These are simple enough operations; we do not need to
call an out-of-line helper.

Tested-by: Edgar E. Iglesias &lt;edgar.iglesias@xilinx.com&gt;
Reviewed-by: Edgar E. Iglesias &lt;edgar.iglesias@xilinx.com&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>target/microblaze: Convert dec_sub to decodetree</title>
<updated>2020-09-01T14:41:38+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2020-08-17T18:29:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=a2b0b90e7960c6dcf52be237149c1b9ff289d9a5'/>
<id>urn:sha1:a2b0b90e7960c6dcf52be237149c1b9ff289d9a5</id>
<content type='text'>
Use tcg_gen_add2_i32 for computing carry.
This removes the last use of helper_carry, so remove that.

Tested-by: Edgar E. Iglesias &lt;edgar.iglesias@xilinx.com&gt;
Reviewed-by: Edgar E. Iglesias &lt;edgar.iglesias@xilinx.com&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>target/microblaze: Remove helper_debug and env-&gt;debug</title>
<updated>2020-09-01T14:41:38+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2020-08-24T13:46:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=eb2022b7d0dcf5be089f9519ac096ebe60b46797'/>
<id>urn:sha1:eb2022b7d0dcf5be089f9519ac096ebe60b46797</id>
<content type='text'>
This is not used, and seems redundant with -d cpu.

Tested-by: Edgar E. Iglesias &lt;edgar.iglesias@xilinx.com&gt;
Reviewed-by: Edgar E. Iglesias &lt;edgar.iglesias@xilinx.com&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>target/microblaze: Mark raise_exception as noreturn</title>
<updated>2020-09-01T14:41:38+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2020-08-25T14:35:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=41060b74bf4597b8260205bf1b6ed43c3b1696d7'/>
<id>urn:sha1:41060b74bf4597b8260205bf1b6ed43c3b1696d7</id>
<content type='text'>
This will allow tcg to remove any dead code that might
follow an exception.

Tested-by: Edgar E. Iglesias &lt;edgar.iglesias@xilinx.com&gt;
Reviewed-by: Edgar E. Iglesias &lt;edgar.iglesias@xilinx.com&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>target-microblaze: Add support for extended access to TLBLO</title>
<updated>2018-05-29T07:35:14+00:00</updated>
<author>
<name>Edgar E. Iglesias</name>
</author>
<published>2018-04-16T19:25:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=f0f7e7f7b284f536389a3c5b67de681055325317'/>
<id>urn:sha1:f0f7e7f7b284f536389a3c5b67de681055325317</id>
<content type='text'>
Add support for extended access to TLBLO's upper 32 bits.

Reviewed-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
Signed-off-by: Edgar E. Iglesias &lt;edgar.iglesias@xilinx.com&gt;
</content>
</entry>
</feed>
