Experimental fork of QEMU with video encoding patches https://git.openslx.org/bwlp/qemu.git/atom/target/microblaze/mmu.h?h=spice_video_codecs 2022-03-06T12:15:42+00:00 2022-03-06T12:15:42+00:00 Philippe Mathieu-Daudé 2022-02-07T11:44:46+00:00 urn:sha1:3cb1a410efb5d246862d7f1c135963fd0a688d70 These target-specific files use the target-specific CPU state but lack to include "cpu.h"; i.e.: ../target/riscv/pmp.h:61:23: error: unknown type name 'CPURISCVState' void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, ^ ../target/nios2/mmu.h:43:18: error: unknown type name 'CPUNios2State' void mmu_flip_um(CPUNios2State *env, unsigned int um); ^ ../target/microblaze/mmu.h:88:19: error: unknown type name 'CPUMBState'; did you mean 'CPUState'? uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn); ^~~~~~~~~~ CPUState Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220214183144.27402-10-f4bug@amsat.org> 2021-01-27T07:32:55+00:00 Joe Komlodi 2021-01-22T00:18:54+00:00 urn:sha1:671a0a1265aeecae6775a8c7b8d6a5ede8a7ad32 Using MMUAccessType makes it more clear what the variable's use is. No functional change. Signed-off-by: Joe Komlodi <komlodi@xilinx.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-Id: <1611274735-303873-3-git-send-email-komlodi@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> 2020-11-15T15:39:21+00:00 Chetan Pant 2020-10-23T12:18:21+00:00 urn:sha1:ee4520364603099bfdda59f43573eebdef2822b5 There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Message-Id: <20201023121821.19179-1-chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> 2020-09-07T19:58:08+00:00 Richard Henderson 2020-09-04T18:31:57+00:00 urn:sha1:de73ee1abe95d37fa1b9c3129cb8a778eea43159 The final 4 fields in MicroBlazeMMU are configuration constants. Move them into MicroBlazeCPUConfig where they belong. Remove the leading "c_" from the member names, as that presumably implied "config", and that should not be explicit in the location. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2020-09-07T19:58:08+00:00 Richard Henderson 2020-09-03T06:18:35+00:00 urn:sha1:8ce97bc188ecebd5030059411b6e29f2cec64dc1 Introduce typedefs and follow CODING_STYLE for naming. Rename struct microblaze_mmu to MicroBlazeMMU. Rename struct microblaze_mmu_lookup to MicroBlazeMMULookup. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2019-06-12T11:20:21+00:00 Markus Armbruster 2019-06-04T18:16:18+00:00 urn:sha1:f91005e195e7e1485e60cb121731589960f1a3c9 Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190604181618.19980-5-armbru@redhat.com> 2018-05-29T07:35:14+00:00 Edgar E. Iglesias 2018-04-16T19:25:01+00:00 urn:sha1:f0f7e7f7b284f536389a3c5b67de681055325317 Add support for extended access to TLBLO's upper 32 bits. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> 2018-05-29T07:35:14+00:00 Edgar E. Iglesias 2018-04-16T17:37:16+00:00 urn:sha1:3924a9aa02fa00a256ddcfe2d6a08bc410ddcaaf Add a configurable output address mask, used to mimic the configurable physical address bit width. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> 2018-05-29T07:35:14+00:00 Edgar E. Iglesias 2018-04-16T19:03:01+00:00 urn:sha1:d2f004c3cdcb786303057683252112c3ff7b337e Prepare for 64-bit addresses. This makes no functional difference as the upper parts of the 64-bit addresses are not yet reachable. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> 2018-05-29T07:35:14+00:00 Edgar E. Iglesias 2018-04-15T21:25:58+00:00 urn:sha1:96716533afa039b4698360af221a8c399367f91d Add explicit handling for MMU_R_TLBX and log accesses to invalid MMU registers. We can now remove the state for all regs but PID, ZPR and TLBX (0 - 2). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>