<feed xmlns='http://www.w3.org/2005/Atom'>
<title>bwlp/qemu.git/target/mips/tcg, branch spice_video_codecs</title>
<subtitle>Experimental fork of QEMU with video encoding patches</subtitle>
<id>https://git.openslx.org/bwlp/qemu.git/atom/target/mips/tcg?h=spice_video_codecs</id>
<link rel='self' href='https://git.openslx.org/bwlp/qemu.git/atom/target/mips/tcg?h=spice_video_codecs'/>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/'/>
<updated>2022-11-08T00:04:25+00:00</updated>
<entry>
<title>target/mips: Don't check COP1X for 64 bit FP mode</title>
<updated>2022-11-08T00:04:25+00:00</updated>
<author>
<name>Jiaxun Yang</name>
</author>
<published>2022-11-02T16:57:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=2a2105a26219695c72bfc7cab9b7d37754fc0920'/>
<id>urn:sha1:2a2105a26219695c72bfc7cab9b7d37754fc0920</id>
<content type='text'>
Some implementations (i.e. Loongson-2F) may decide to implement
a 64 bit FPU without implementing COP1X instructions.

As the eligibility of 64 bit FP instructions is already determined
by CP0St_FR, there is no need to check for COP1X again.

Signed-off-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
Message-Id: &lt;20221102165719.190378-1-jiaxun.yang@flygoat.com&gt;
[PMD: Add missing trailing parenthesis (buildfix)]
Signed-off-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
</content>
</entry>
<entry>
<title>target/mips: Enable LBX/LWX/* instructions for Octeon</title>
<updated>2022-11-08T00:04:25+00:00</updated>
<author>
<name>Pavel Dovgalyuk</name>
</author>
<published>2022-11-01T05:29:44+00:00</published>
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<id>urn:sha1:4525ea7e0caa4aa6317204cd977179dea972cf6d</id>
<content type='text'>
This patch changes condition and function name for enabling
indexed load instructions for Octeon vCPUs. Octeons do not
have DSP extension, but implement LBX-and-others.

Signed-off-by: Pavel Dovgalyuk &lt;Pavel.Dovgalyuk@ispras.ru&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
Message-Id: &lt;166728058455.229236.13834649461181619195.stgit@pasha-ThinkPad-X280&gt;
Signed-off-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
</content>
</entry>
<entry>
<title>target/mips: Cast offset field of Octeon BBIT to int16_t</title>
<updated>2022-11-08T00:04:25+00:00</updated>
<author>
<name>Jiaxun Yang</name>
</author>
<published>2022-10-31T13:25:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=0e8b3010afa7507f42754ebec16bbd4dfdb3a660'/>
<id>urn:sha1:0e8b3010afa7507f42754ebec16bbd4dfdb3a660</id>
<content type='text'>
As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference
Manual" offset field is signed 16 bit value. However arg_BBIT.offset
is unsigned. We need to cast it as signed to do address calculation.

Signed-off-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
Acked-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Acked-by: Pavel Dovgalyuk &lt;Pavel.Dovgalyuk@ispras.ru&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
Message-Id: &lt;20221031132531.18122-3-jiaxun.yang@flygoat.com&gt;
Signed-off-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
</content>
</entry>
<entry>
<title>target/mips: Convert to tcg_ops restore_state_to_opc</title>
<updated>2022-10-26T01:11:28+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-10-24T10:35:06+00:00</published>
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<id>urn:sha1:3766855c9b729411ac898fe874cecf6f44a7eecf</id>
<content type='text'>
Reviewed-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>accel/tcg: Introduce tb_pc and log_pc</title>
<updated>2022-10-04T19:13:12+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-08-15T20:16:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=fbf59aad178d98afe193fa872a2d880266a75269'/>
<id>urn:sha1:fbf59aad178d98afe193fa872a2d880266a75269</id>
<content type='text'>
The availability of tb-&gt;pc will shortly be conditional.
Introduce accessor functions to minimize ifdefs.

Pass around a known pc to places like tcg_gen_code,
where the caller must already have the value.

Reviewed-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>target/mips: Honour -semihosting-config userspace=on</title>
<updated>2022-09-13T16:18:21+00:00</updated>
<author>
<name>Peter Maydell</name>
</author>
<published>2022-08-22T14:12:27+00:00</published>
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<id>urn:sha1:b35d74015b0262260b7dbb75c80ea85aeebab89b</id>
<content type='text'>
Honour the commandline -semihosting-config userspace=on option,
instead of always permitting userspace semihosting calls in system
emulation mode, by passing the correct value to the is_userspace
argument of semihosting_enabled().

Note that this is a behaviour change: if the user wants to
do semihosting calls from userspace they must now specifically
enable them on the command line.

MIPS semihosting is not implemented for linux-user builds.

Signed-off-by: Peter Maydell &lt;peter.maydell@linaro.org&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-Id: &lt;20220822141230.3658237-5-peter.maydell@linaro.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>accel/tcg: Add pc and host_pc params to gen_intermediate_code</title>
<updated>2022-09-06T07:04:26+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-08-11T20:48:03+00:00</published>
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<id>urn:sha1:306c872103b4d0986c9f671eb7538b0b70bf69b5</id>
<content type='text'>
Pass these along to translator_loop -- pc may be used instead
of tb-&gt;pc, and host_pc is currently unused.  Adjust all targets
at one time.

Acked-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
Acked-by: Ilya Leoshkevich &lt;iii@linux.ibm.com&gt;
Tested-by: Ilya Leoshkevich &lt;iii@linux.ibm.com&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>target/mips: Handle lock_user() failure in UHI_plog semihosting call</title>
<updated>2022-08-08T21:22:36+00:00</updated>
<author>
<name>Peter Maydell</name>
</author>
<published>2022-07-19T19:17:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=8809baf4e40633ba01b47cd2257bbbbba14fc861'/>
<id>urn:sha1:8809baf4e40633ba01b47cd2257bbbbba14fc861</id>
<content type='text'>
Coverity notes that we forgot to check the error return from
lock_user() in one place in the handling of the UHI_plog semihosting
call.  Add the missing error handling.

report_fault() is rather brutal in that it will call abort(), but
this is the same error-handling used in the rest of this file.

Resolves: Coverity CID 1490684
Fixes: ea4210600db3c5 ("target/mips: Avoid qemu_semihosting_log_out for UHI_plog")
Signed-off-by: Peter Maydell &lt;peter.maydell@linaro.org&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Message-Id: &lt;20220719191737.384744-1-peter.maydell@linaro.org&gt;
Signed-off-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
</content>
</entry>
<entry>
<title>target/mips: Advance pc after semihosting exception</title>
<updated>2022-08-02T19:34:00+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-07-30T02:17:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=d44971e725c02e0656d2f53d4fb564f92e06aef7'/>
<id>urn:sha1:d44971e725c02e0656d2f53d4fb564f92e06aef7</id>
<content type='text'>
Delay generating the exception until after we know the
insn length, and record that length in env-&gt;error_code.

Fixes: 8ec7e3c53d4 ("target/mips: Use an exception for semihosting")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1126
Reviewed-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>target/mips: Remove GET_TARGET_STRING and FREE_TARGET_STRING</title>
<updated>2022-07-12T20:32:22+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-06-28T11:17:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=b10ccec10096a27bb3b99a7291d5a3d5c826a1f3'/>
<id>urn:sha1:b10ccec10096a27bb3b99a7291d5a3d5c826a1f3</id>
<content type='text'>
Inline these macros into the only two callers.

Reviewed-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-Id: &lt;20220628111701.677216-9-richard.henderson@linaro.org&gt;
Signed-off-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
</content>
</entry>
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