bwlp/qemu.git/target/ppc/cpu.c, branch spice_video_codecs

target/ppc: introduce ppc_maybe_interrupt

2022-10-28T16:15:22+00:00

This new method will check if any pending interrupt was unmasked and then call cpu_interrupt/cpu_reset_interrupt accordingly. Code that raises/lowers or masks/unmasks interrupts should call this method to keep CPU_INTERRUPT_HARD coherent with env->pending_interrupts. Signed-off-by: Matheus Ferst Reviewed-by: Daniel Henrique Barboza Message-Id: <20221021142156.4134411-2-matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza

target/ppc: remove ppc_store_lpcr from CONFIG_USER_ONLY builds

2022-10-28T16:15:22+00:00

Writes to LPCR are hypervisor privileged. Signed-off-by: Matheus Ferst Reviewed-by: Fabiano Rosas Message-Id: <20221011204829.1641124-27-matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza

target/ppc: Bugfix FP when OE/UE are set

2022-08-31T17:08:05+00:00

When an overflow exception occurs and OE is set the intermediate result should be adjusted (by subtracting from the exponent) to avoid rounding to inf. The same applies to an underflow exceptionion and UE (but adding to the exponent). To do this set the fp_status.rebias_overflow when OE is set and fp_status.rebias_underflow when UE is set as the FPU will recalculate in case of a overflow/underflow if the according rebias* is set. Signed-off-by: Lucas Mateus Castro (alqotel) Reviewed-by: Richard Henderson Message-Id: <20220805141522.412864-3-lucas.araujo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza

target/ppc: Remove fpscr_* macros from cpu.h

2022-05-05T18:36:17+00:00

fpscr_* defined macros are hiding the usage of *env behind them. Substitute the usage of these macros with `env->fpscr & FP_*` to make the code cleaner. Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Víctor Colombo Message-Id: <20220504210541.115256-2-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza

target/ppc: ppc_store_fpscr doesn't update bits 0 to 28 and 52

2021-12-17T16:57:13+00:00

This commit fixes the difference reported in the bug in the reserved bit 52, it does this by adding this bit to the mask of bits to not be directly altered in the ppc_store_fpscr function (the hardware used to compare to QEMU was a Power9). The bits 0 to 27 were also added to the mask, as they are marked as reserved in the PowerISA and bit 28 is a reserved extension of the DRN field (bits 29:31) but can't be set using mtfsfi, while the other DRN bits may be set using mtfsfi instruction, so bit 28 was also added to the mask. Although this is a difference reported in the bug, since it's a reserved bit it may be a "don't care" case, as put in the bug report. Looking at the ISA it doesn't explicitly mention this bit can't be set, like it does for FEX and VX, so I'm unsure if this is necessary. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/266 Signed-off-by: Lucas Mateus Castro (alqotel) Message-Id: <20211201163808.440385-4-lucas.araujo@eldorado.org.br> Signed-off-by: Cédric Le Goater

linux-user: Fix XER access in ppc version of elf_core_copy_regs

2021-10-21T00:42:47+00:00

env->xer doesn't hold some bits of XER, like OV and CA. To write the complete register in the core dump we should read XER value with cpu_read_xer. Reported-by: Lucas Mateus Castro (alqotel) Fixes: da91a00f191f ("target-ppc: Split out SO, OV, CA fields from XER") Signed-off-by: Matheus Ferst Message-Id: <20211014223234.127012-4-matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson Signed-off-by: David Gibson

target/ppc: moved ppc_store_sdr1 to mmu_common.c

2021-08-27T02:41:13+00:00

ppc_store_sdr1 was at first in mmu_helper.c and was moved as part the patches to enable the disable-tcg option, now it's being moved back to a file that will be compiled with that option Signed-off-by: Lucas Mateus Castro (alqotel) Message-Id: <20210723175627.72847-3-lucas.araujo@eldorado.org.br> Signed-off-by: David Gibson

target/ppc: Allow virtual hypervisor on CPU without HV

2021-07-09T00:38:19+00:00

Change the assert in ppc_store_sdr1() to allow vhyp to be set on CPUs without HV bit. This allows using the vhyp interface for firmware emulation on pegasos2. Signed-off-by: BALATON Zoltan Message-Id: <21c7745aabbb68fcc50bb2ffaf16b939ba21261c.1624811233.git.balaton@eik.bme.hu> Signed-off-by: David Gibson

target/ppc: overhauled and moved logic of storing fpscr

2021-06-03T08:10:31+00:00

Followed the suggested overhaul to store_fpscr logic, and moved it to cpu.c where it can be accessed in !TCG builds. The overhaul was suggested because storing a value to fpscr should never raise an exception, so we could remove all the mess that happened with POWERPC_EXCP_FP. We also moved fpscr_set_rounding_mode into cpu.c as it could now be moved there, and it is needed when a value for the fpscr is being stored directly. Suggested-by: Richard Henderson Signed-off-by: Bruno Larsen (billionai) Reviewed-by: Richard Henderson Message-Id: <20210527163522.23019-1-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson

target/ppc: moved ppc_store_lpcr and ppc_store_msr to cpu.c

2021-06-03T03:22:06+00:00

These functions are used in hw/ppc logic, during machine startup, which means it must be compiled when --disable-tcg is selected, and so it has been moved into a common code file Signed-off-by: Bruno Larsen (billionai) Reviewed-by: Richard Henderson Reviewed-by: David Gibson Message-Id: <20210521201759.85475-3-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson