bwlp/qemu.git/target/ppc/internal.h, branch spice_video_codecs

target/ppc: Implement new wait variants

2022-07-28T16:30:41+00:00

ISA v2.06 adds new variations of wait, specified by the WC field. These are not all compatible with the prior wait implementation, because they add additional conditions that cause the processor to resume, which can cause software to hang or run very slowly. At this moment, with the current wait implementation and a pseries guest using mainline kernel with new wait upcodes [1], QEMU hangs during boot if more than one CPU is present: qemu-system-ppc64 -M pseries,x-vof=on -cpu POWER10 -smp 2 -nographic -kernel zImage.pseries -no-reboot QEMU will exit (as there's no filesystem) if the test "passes", or hang during boot if it hits the bug. ISA v3.0 changed the wait opcode and removed the new variants (retaining the WC field but making non-zero values reserved). ISA v3.1 added new WC values to the new wait opcode, and added a PL field. This patch implements the new wait encoding and supports WC variants with no-op implementations, which provides basic correctness as explained in comments. [1] https://lore.kernel.org/all/20220720132132.903462-1-npiggin@gmail.com/ Signed-off-by: Nicholas Piggin Reviewed-by: Víctor Colombo Tested-by: Joel Stanley Reviewed-by: Daniel Henrique Barboza Message-Id: <20220720133352.904263-1-npiggin@gmail.com> [danielhb: added information about the bug being fixed] Signed-off-by: Daniel Henrique Barboza

target/ppc: Move mffscrn[i] to decodetree

2022-07-06T13:22:38+00:00

Signed-off-by: Víctor Colombo Reviewed-by: Matheus Ferst Message-Id: <20220629162904.105060-3-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza

target/ppc: Implemented xviger instructions

2022-05-26T20:11:33+00:00

Implement the following PowerISA v3.1 instructions: xvi4ger8: VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) xvi4ger8pp: VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) Positive multiply, Positive accumulate xvi8ger4: VSX Vector 4-bit Signed Integer GER (rank-8 update) xvi8ger4pp: VSX Vector 4-bit Signed Integer GER (rank-8 update) Positive multiply, Positive accumulate xvi8ger4spp: VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) with Saturate Positive multiply, Positive accumulate xvi16ger2: VSX Vector 16-bit Signed Integer GER (rank-2 update) xvi16ger2pp: VSX Vector 16-bit Signed Integer GER (rank-2 update) Positive multiply, Positive accumulate xvi16ger2s: VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation xvi16ger2spp: VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation Positive multiply, Positive accumulate Signed-off-by: Lucas Mateus Castro (alqotel) Reviewed-by: Richard Henderson Message-Id: <20220524140537.27451-3-lucas.araujo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza

compiler.h: replace QEMU_NORETURN with G_NORETURN

2022-04-21T13:03:51+00:00

G_NORETURN was introduced in glib 2.68, fallback to G_GNUC_NORETURN in glib-compat. Note that this attribute must be placed before the function declaration (bringing a bit of consistency in qemu codebase usage). Signed-off-by: Marc-André Lureau Reviewed-by: Daniel P. Berrangé Reviewed-by: Warner Losh Message-Id: <20220420132624.2439741-20-marcandre.lureau@redhat.com>

target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu

2021-11-02T11:00:52+00:00

This is not used by, nor required by, user-only. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson

target/ppc: Implement ppc_cpu_record_sigsegv

2021-11-02T11:00:52+00:00

Record DAR, DSISR, and exception_index. That last means that we must exit to cpu_loop ourselves, instead of letting exception_index being overwritten. This is exactly what the user-mode ppc_cpu_tlb_fill does, so simply rename it as ppc_cpu_record_sigsegv. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson

hw/core: Make do_unaligned_access noreturn

2021-09-22T02:36:44+00:00

While we may have had some thought of allowing system-mode to return from this hook, we have no guests that require this. Reviewed-by: Alistair Francis Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson

target/ppc: divided mmu_helper.c in 2 files

2021-08-27T02:41:13+00:00

Divided mmu_helper.c in 2 files, functions inside #ifdef CONFIG_SOFTMMU stayed in mmu_helper.c, other functions moved to mmu_common.c. Updated meson.build to compile mmu_common.c and only compile mmu_helper.c when CONFIG_TCG is set. Moved function declarations, #define and structs used by both files to internal.h except for functions that use structures defined in cpu.h, those were moved to cpu.h. Signed-off-by: Lucas Mateus Castro (alqotel) Message-Id: <20210723175627.72847-2-lucas.araujo@eldorado.org.br> Signed-off-by: David Gibson

target/ppc: removed all mentions to PPC_DUMP_CPU

2021-06-03T08:10:31+00:00

This feature will no longer be useful as ppc moves to using decodetree for TCG. And building with it enabled is no longer possible, due to changes in opc_handler_t. Since the last commit that mentions it happened in 2014, I think it is safe to remove it. Signed-off-by: Bruno Larsen (billionai) Message-Id: <20210531145629.21300-5-bruno.larsen@eldorado.org.br> Reviewed-by: Luis Pires Reviewed-by: Richard Henderson Signed-off-by: David Gibson

target/ppc: Introduce prot_for_access_type

2021-05-19T02:50:47+00:00

Use this in the three places we currently have a local array indexed by rwx (which happens to have the same values). The types will match up correctly with additional changes. Signed-off-by: Richard Henderson Message-Id: <20210518201146.794854-2-richard.henderson@linaro.org> Signed-off-by: David Gibson