<feed xmlns='http://www.w3.org/2005/Atom'>
<title>bwlp/qemu.git/target/rx/cpu.c, branch spice_video_codecs</title>
<subtitle>Experimental fork of QEMU with video encoding patches</subtitle>
<id>https://git.openslx.org/bwlp/qemu.git/atom/target/rx/cpu.c?h=spice_video_codecs</id>
<link rel='self' href='https://git.openslx.org/bwlp/qemu.git/atom/target/rx/cpu.c?h=spice_video_codecs'/>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/'/>
<updated>2022-10-26T01:11:28+00:00</updated>
<entry>
<title>target/rx: Convert to tcg_ops restore_state_to_opc</title>
<updated>2022-10-26T01:11:28+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-10-24T10:52:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=5439d7a68ce3449d4091e0b4c084579b9467a683'/>
<id>urn:sha1:5439d7a68ce3449d4091e0b4c084579b9467a683</id>
<content type='text'>
Reviewed-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>accel/tcg: Introduce tb_pc and log_pc</title>
<updated>2022-10-04T19:13:12+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-08-15T20:16:06+00:00</published>
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<id>urn:sha1:fbf59aad178d98afe193fa872a2d880266a75269</id>
<content type='text'>
The availability of tb-&gt;pc will shortly be conditional.
Introduce accessor functions to minimize ifdefs.

Pass around a known pc to places like tcg_gen_code,
where the caller must already have the value.

Reviewed-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>hw/core: Add CPUClass.get_pc</title>
<updated>2022-10-04T19:13:12+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-09-30T17:31:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=e4fdf9df5b1c2aa427de796bea973520027ddd15'/>
<id>urn:sha1:e4fdf9df5b1c2aa427de796bea973520027ddd15</id>
<content type='text'>
Populate this new method for all targets.  Always match
the result that would be given by cpu_get_tb_cpu_state,
as we will want these values to correspond in the logs.

Reviewed-by: Taylor Simpson &lt;tsimpson@quicinc.com&gt;
Reviewed-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Reviewed-by: Mark Cave-Ayland &lt;mark.cave-ayland@ilande.co.uk&gt; (target/sparc)
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
---
Cc: Eduardo Habkost &lt;eduardo@habkost.net&gt; (supporter:Machine core)
Cc: Marcel Apfelbaum &lt;marcel.apfelbaum@gmail.com&gt; (supporter:Machine core)
Cc: "Philippe Mathieu-Daudé" &lt;f4bug@amsat.org&gt; (reviewer:Machine core)
Cc: Yanan Wang &lt;wangyanan55@huawei.com&gt; (reviewer:Machine core)
Cc: Michael Rolnik &lt;mrolnik@gmail.com&gt; (maintainer:AVR TCG CPUs)
Cc: "Edgar E. Iglesias" &lt;edgar.iglesias@gmail.com&gt; (maintainer:CRIS TCG CPUs)
Cc: Taylor Simpson &lt;tsimpson@quicinc.com&gt; (supporter:Hexagon TCG CPUs)
Cc: Song Gao &lt;gaosong@loongson.cn&gt; (maintainer:LoongArch TCG CPUs)
Cc: Xiaojuan Yang &lt;yangxiaojuan@loongson.cn&gt; (maintainer:LoongArch TCG CPUs)
Cc: Laurent Vivier &lt;laurent@vivier.eu&gt; (maintainer:M68K TCG CPUs)
Cc: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt; (reviewer:MIPS TCG CPUs)
Cc: Aleksandar Rikalo &lt;aleksandar.rikalo@syrmia.com&gt; (reviewer:MIPS TCG CPUs)
Cc: Chris Wulff &lt;crwulff@gmail.com&gt; (maintainer:NiosII TCG CPUs)
Cc: Marek Vasut &lt;marex@denx.de&gt; (maintainer:NiosII TCG CPUs)
Cc: Stafford Horne &lt;shorne@gmail.com&gt; (odd fixer:OpenRISC TCG CPUs)
Cc: Yoshinori Sato &lt;ysato@users.sourceforge.jp&gt; (reviewer:RENESAS RX CPUs)
Cc: Mark Cave-Ayland &lt;mark.cave-ayland@ilande.co.uk&gt; (maintainer:SPARC TCG CPUs)
Cc: Bastian Koppelmann &lt;kbastian@mail.uni-paderborn.de&gt; (maintainer:TriCore TCG CPUs)
Cc: Max Filippov &lt;jcmvbkbc@gmail.com&gt; (maintainer:Xtensa TCG CPUs)
Cc: qemu-arm@nongnu.org (open list:ARM TCG CPUs)
Cc: qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs)
Cc: qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs)
Cc: qemu-s390x@nongnu.org (open list:S390 TCG CPUs)
</content>
</entry>
<entry>
<title>Remove qemu-common.h include from most units</title>
<updated>2022-04-06T12:31:55+00:00</updated>
<author>
<name>Marc-André Lureau</name>
</author>
<published>2022-03-23T15:57:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=0f9668e0c197ab6de95f61a906703a1d127c11f8'/>
<id>urn:sha1:0f9668e0c197ab6de95f61a906703a1d127c11f8</id>
<content type='text'>
Signed-off-by: Marc-André Lureau &lt;marcandre.lureau@redhat.com&gt;
Message-Id: &lt;20220323155743.1585078-33-marcandre.lureau@redhat.com&gt;
Signed-off-by: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
</content>
</entry>
<entry>
<title>target/rx: Restrict cpu_exec_interrupt() handler to sysemu</title>
<updated>2021-09-14T19:00:21+00:00</updated>
<author>
<name>Philippe Mathieu-Daudé</name>
</author>
<published>2021-09-11T16:54:31+00:00</published>
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<id>urn:sha1:65c575b61e000ef862f899643ed0a818794881b9</id>
<content type='text'>
Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Reviewed-by: Warner Losh &lt;imp@bsdimp.com&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-Id: &lt;20210911165434.531552-22-f4bug@amsat.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>hw/core: Constify TCGCPUOps</title>
<updated>2021-05-26T22:33:59+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2021-02-27T23:21:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=119065574d02deffc28fe5b6a864db9b467c6ffd'/>
<id>urn:sha1:119065574d02deffc28fe5b6a864db9b467c6ffd</id>
<content type='text'>
We no longer have any runtime modifications to this struct,
so declare them all const.

Tested-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-ID: &lt;20210227232519.222663-3-richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps</title>
<updated>2021-05-26T22:33:59+00:00</updated>
<author>
<name>Philippe Mathieu-Daudé</name>
</author>
<published>2021-05-17T10:51:37+00:00</published>
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<id>urn:sha1:08928c6d0db7d554ef041256e52330bb257bc70f</id>
<content type='text'>
Signed-off-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-Id: &lt;20210517105140.1062037-21-f4bug@amsat.org&gt;
[rth: Drop declaration movement from target/*/cpu.h]
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>cpu: Introduce SysemuCPUOps structure</title>
<updated>2021-05-26T22:33:59+00:00</updated>
<author>
<name>Philippe Mathieu-Daudé</name>
</author>
<published>2021-05-17T10:51:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=8b80bd28a5cf8d8af7d38abcf1c7d81a1b226ec3'/>
<id>urn:sha1:8b80bd28a5cf8d8af7d38abcf1c7d81a1b226ec3</id>
<content type='text'>
Introduce a structure to hold handler specific to sysemu.

Signed-off-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-Id: &lt;20210517105140.1062037-15-f4bug@amsat.org&gt;
[rth: Squash "restrict hw/core/sysemu-cpu-ops.h" patch]
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass</title>
<updated>2021-02-05T20:24:15+00:00</updated>
<author>
<name>Claudio Fontana</name>
</author>
<published>2021-02-04T16:39:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=78271684719f34c1cc19f895e089f2f19b69698d'/>
<id>urn:sha1:78271684719f34c1cc19f895e089f2f19b69698d</id>
<content type='text'>
we cannot in principle make the TCG Operations field definitions
conditional on CONFIG_TCG in code that is included by both common_ss
and specific_ss modules.

Therefore, what we can do safely to restrict the TCG fields to TCG-only
builds, is to move all tcg cpu operations into a separate header file,
which is only included by TCG, target-specific code.

This leaves just a NULL pointer in the cpu.h for the non-TCG builds.

This also tidies up the code in all targets a bit, having all TCG cpu
operations neatly contained by a dedicated data struct.

Signed-off-by: Claudio Fontana &lt;cfontana@suse.de&gt;
Message-Id: &lt;20210204163931.7358-16-cfontana@suse.de&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>cpu: move cc-&gt;do_interrupt to tcg_ops</title>
<updated>2021-02-05T20:24:14+00:00</updated>
<author>
<name>Claudio Fontana</name>
</author>
<published>2021-02-04T16:39:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=0545608056a6161e7020cd7b9368d9636fa80051'/>
<id>urn:sha1:0545608056a6161e7020cd7b9368d9636fa80051</id>
<content type='text'>
Signed-off-by: Claudio Fontana &lt;cfontana@suse.de&gt;
Reviewed-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-Id: &lt;20210204163931.7358-10-cfontana@suse.de&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
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