bwlp/qemu.git/target/rx, branch spice_video_codecs

Merge tag 'pull-tcg-20221026' of https://gitlab.com/rth7680/qemu into staging

2022-10-26T14:53:41+00:00

Revert incorrect cflags initialization. Add direct jumps for tcg/loongarch64. Speed up breakpoint check. Improve assertions for atomic.h. Move restore_state_to_opc to TCGCPUOps. Cleanups to TranslationBlock maintenance. # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmNYlo4dHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9y2wf9EKsCA6VtYI2Qtftf # q/ujYFmUf8AKTb9eVcA0XX71CT1dEnFR7GQyT8B8X13x0pSbOX7tbEWHPreegTFV # tESiejvymi6Q9devAB58GVwNoU/zPIQQGhCPxkVUKDmRztJz22MbGUzd7UKPPgU8 # 2nVMkIpLTMBsKeFLxE/D3ZntmdKsgyI/1Dtkl9TxvlDGsCbMjbNcr8lM+TLaG2oX # GZhFyJHKEVy0cobukvhhb/9rU7AWdG/BnFmZM16JxvHV/YCwJBx3Udhcy9xPePUU # yIjkGsUAq4aB6H9RFuTWh7GmaY5u6gMbTTi2J7hDos0mzauYJtpgEB/H42LpycGE # sOhkLQ== # =DUb8 # -----END PGP SIGNATURE----- # gpg: Signature made Tue 25 Oct 2022 22:08:14 EDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson " [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20221026' of https://gitlab.com/rth7680/qemu: (47 commits) accel/tcg: Remove restore_state_to_opc function target/xtensa: Convert to tcg_ops restore_state_to_opc target/tricore: Convert to tcg_ops restore_state_to_opc target/sparc: Convert to tcg_ops restore_state_to_opc target/sh4: Convert to tcg_ops restore_state_to_opc target/s390x: Convert to tcg_ops restore_state_to_opc target/rx: Convert to tcg_ops restore_state_to_opc target/riscv: Convert to tcg_ops restore_state_to_opc target/ppc: Convert to tcg_ops restore_state_to_opc target/openrisc: Convert to tcg_ops restore_state_to_opc target/nios2: Convert to tcg_ops restore_state_to_opc target/mips: Convert to tcg_ops restore_state_to_opc target/microblaze: Convert to tcg_ops restore_state_to_opc target/m68k: Convert to tcg_ops restore_state_to_opc target/loongarch: Convert to tcg_ops restore_state_to_opc target/i386: Convert to tcg_ops restore_state_to_opc target/hppa: Convert to tcg_ops restore_state_to_opc target/hexagon: Convert to tcg_ops restore_state_to_opc target/cris: Convert to tcg_ops restore_state_to_opc target/avr: Convert to tcg_ops restore_state_to_opc ... Signed-off-by: Stefan Hajnoczi

target/rx: Convert to tcg_ops restore_state_to_opc

2022-10-26T01:11:28+00:00

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson

treewide: Remove the unnecessary space before semicolon

2022-10-24T11:41:10+00:00

%s/return ;/return; Signed-off-by: Bin Meng Reviewed-by: Peter Maydell Reviewed-by: Christian Schoenebeck Message-Id: <20221024072802.457832-1-bmeng@tinylab.org> Signed-off-by: Laurent Vivier

accel/tcg: Introduce tb_pc and log_pc

2022-10-04T19:13:12+00:00

The availability of tb->pc will shortly be conditional. Introduce accessor functions to minimize ifdefs. Pass around a known pc to places like tcg_gen_code, where the caller must already have the value. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson

hw/core: Add CPUClass.get_pc

2022-10-04T19:13:12+00:00

Populate this new method for all targets. Always match the result that would be given by cpu_get_tb_cpu_state, as we will want these values to correspond in the logs. Reviewed-by: Taylor Simpson Reviewed-by: Alex Bennée Reviewed-by: Mark Cave-Ayland (target/sparc) Signed-off-by: Richard Henderson --- Cc: Eduardo Habkost (supporter:Machine core) Cc: Marcel Apfelbaum (supporter:Machine core) Cc: "Philippe Mathieu-Daudé" (reviewer:Machine core) Cc: Yanan Wang (reviewer:Machine core) Cc: Michael Rolnik (maintainer:AVR TCG CPUs) Cc: "Edgar E. Iglesias" (maintainer:CRIS TCG CPUs) Cc: Taylor Simpson (supporter:Hexagon TCG CPUs) Cc: Song Gao (maintainer:LoongArch TCG CPUs) Cc: Xiaojuan Yang (maintainer:LoongArch TCG CPUs) Cc: Laurent Vivier (maintainer:M68K TCG CPUs) Cc: Jiaxun Yang (reviewer:MIPS TCG CPUs) Cc: Aleksandar Rikalo (reviewer:MIPS TCG CPUs) Cc: Chris Wulff (maintainer:NiosII TCG CPUs) Cc: Marek Vasut (maintainer:NiosII TCG CPUs) Cc: Stafford Horne (odd fixer:OpenRISC TCG CPUs) Cc: Yoshinori Sato (reviewer:RENESAS RX CPUs) Cc: Mark Cave-Ayland (maintainer:SPARC TCG CPUs) Cc: Bastian Koppelmann (maintainer:TriCore TCG CPUs) Cc: Max Filippov (maintainer:Xtensa TCG CPUs) Cc: qemu-arm@nongnu.org (open list:ARM TCG CPUs) Cc: qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs) Cc: qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Cc: qemu-s390x@nongnu.org (open list:S390 TCG CPUs)

accel/tcg: Add pc and host_pc params to gen_intermediate_code

2022-09-06T07:04:26+00:00

Pass these along to translator_loop -- pc may be used instead of tb->pc, and host_pc is currently unused. Adjust all targets at one time. Acked-by: Alistair Francis Acked-by: Ilya Leoshkevich Tested-by: Ilya Leoshkevich Signed-off-by: Richard Henderson

Merge tag 'pull-rx-20220421' of https://gitlab.com/rth7680/qemu into staging

2022-04-21T23:45:41+00:00

Fix usp/isp swapping upon clrpsw/setpsw. Fix psw.i/pc upon wait. Align dtb in ram. # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmJhlJYdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/ipQf+JLeXW1HaD5iNnyUl # Uh0CLvwwkXvuiDAlaoGCKl2mcVJR/2d/ScTPTGx44VEwmLpV2mgF8/VUWoRtao/C # Kal5DsaOAC2pUKkYbnorsCpq4ty2QMPYXZXOKULPcfLa3tbsr9bE6JkCQ6gZeAAk # ITuB+dfdBTpW2lc0eoQ7cDMcQkD1cxyfNVwZ7rP2i9N6tjTW1488kxsBthhQIr0t # sNrrBIiK7nhdgXNfhWDPP/6f8osZwhLGO8G9tyOTtkPOF6o6Dy27B0Bmlf5T6OY+ # SeTwC2O197gd0YkPWvZgMQbJWnX0kHgHwlFEBaMSxMXAcrlccNZQMyBN4cYoC+ie # e3vyWA== # =lj1s # -----END PGP SIGNATURE----- # gpg: Signature made Thu 21 Apr 2022 10:29:58 AM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson " [ultimate] * tag 'pull-rx-20220421' of https://gitlab.com/rth7680/qemu: target/rx: update PC correctly in wait instruction target/rx: set PSW.I when executing wait instruction hw/rx: rx-gdbsim DTB load address aligned of 16byte. target/rx: Swap stack pointers on clrpsw/setpsw instruction target/rx: Move DISAS_UPDATE check for write to PSW target/rx: Store PSW.U in tb->flags target/rx: Put tb_flags into DisasContext Signed-off-by: Richard Henderson

target/rx: update PC correctly in wait instruction

2022-04-21T17:09:12+00:00

`cpu_pc` at this point does not necessary point to the current instruction (i.e., the wait instruction being translated), so it's incorrect to calculate the new value of `cpu_pc` based on this. It must be updated with `ctx->base.pc_next`, which contains the correct address of the next instruction. This change fixes the wait instruction skipping the subsequent branch when used in an idle loop like this: 0: wait bra.b 0b brk // should be unreachable Signed-off-by: Tomoaki Kawada Reviewed-by: Yoshinori Sato Reviewed-by: Richard Henderson Message-Id: <20220417060224.2131788-1-i@yvt.jp> Signed-off-by: Richard Henderson

target/rx: set PSW.I when executing wait instruction

2022-04-21T17:08:05+00:00

This patch fixes the implementation of the wait instruction to implicitly update PSW.I as required by the ISA specification. Signed-off-by: Tomoaki Kawada Reviewed-by: Yoshinori Sato Reviewed-by: Richard Henderson Message-Id: <20220417045937.2128699-1-i@yvt.jp> Signed-off-by: Richard Henderson

target/rx: Swap stack pointers on clrpsw/setpsw instruction

2022-04-21T17:04:34+00:00

We properly perform this swap in helper_set_psw for MVTC, but we missed doing so for the CLRPSW/SETPSW of the U bit. Reported-by: Tomoaki Kawada Signed-off-by: Richard Henderson Reviewed-by: Yoshinori Sato Message-Id: <20220417165130.695085-5-richard.henderson@linaro.org>