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<title>bwlp/qemu.git/target/s390x/insn-format.def, branch spice_video_codecs</title>
<subtitle>Experimental fork of QEMU with video encoding patches</subtitle>
<id>https://git.openslx.org/bwlp/qemu.git/atom/target/s390x/insn-format.def?h=spice_video_codecs</id>
<link rel='self' href='https://git.openslx.org/bwlp/qemu.git/atom/target/s390x/insn-format.def?h=spice_video_codecs'/>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/'/>
<updated>2021-07-07T12:01:56+00:00</updated>
<entry>
<title>target/s390x: start moving TCG-only code to tcg/</title>
<updated>2021-07-07T12:01:56+00:00</updated>
<author>
<name>Cho, Yu-Chen</name>
</author>
<published>2021-07-07T10:53:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=c9274b6bf0571ecbaaed3e9c3b229e17607a0ea2'/>
<id>urn:sha1:c9274b6bf0571ecbaaed3e9c3b229e17607a0ea2</id>
<content type='text'>
move everything related to translate, as well as HELPER code in tcg/

mmu_helper.c stays put for now, as it contains both TCG and KVM code.

After the reshuffling, update MAINTAINERS accordingly.
Make use of the new directory:

target/s390x/tcg/

Signed-off-by: Claudio Fontana &lt;cfontana@suse.de&gt;
Signed-off-by: Cho, Yu-Chen &lt;acho@suse.com&gt;
Acked-by: David Hildenbrand &lt;david@redhat.com&gt;
Acked-by: Cornelia Huck &lt;cohuck@redhat.com&gt;
Reviewed-by: Thomas Huth &lt;thuth@redhat.com&gt;
Message-Id: &lt;20210707105324.23400-8-acho@suse.com&gt;
Signed-off-by: Cornelia Huck &lt;cohuck@redhat.com&gt;
</content>
</entry>
<entry>
<title>s390x/tcg: Define vector instruction formats</title>
<updated>2019-03-11T08:31:01+00:00</updated>
<author>
<name>David Hildenbrand</name>
</author>
<published>2019-03-07T12:15:08+00:00</published>
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<id>urn:sha1:481accd4f52496a86aa347c8c5de01765a388f83</id>
<content type='text'>
These are the new instruction formats related to vector instructions as
up to the z14 (a.k.a. latest PoP).

As v2 appeares (like x2 in VRX) with d2/b2 in VRV, we have to assign it a
higher field number to avoid collisions.

Properly take care of the MSB (to be able to address 32 registers) for
each vector register field stored in the RXB field (Bit 36 - 30  for all
vector instructions). As we have 32 bit vector registers and the
"v" fields are only 4 bit in size, the 5th bit is stored in the RXB.
We use a new type to indicate that the MSB has to be fetched from the
RXB.

Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Signed-off-by: David Hildenbrand &lt;david@redhat.com&gt;
Message-Id: &lt;20190307121539.12842-2-david@redhat.com&gt;
Signed-off-by: Cornelia Huck &lt;cohuck@redhat.com&gt;
</content>
</entry>
<entry>
<title>s390x/tcg: RXE has an optional M3 field</title>
<updated>2019-03-04T10:49:31+00:00</updated>
<author>
<name>David Hildenbrand</name>
</author>
<published>2019-02-25T20:03:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=5cf955066515df9f948947fce668a05ca6164e14'/>
<id>urn:sha1:5cf955066515df9f948947fce668a05ca6164e14</id>
<content type='text'>
Will be needed, so add it to the format description.

Reviewed-by: Thomas Huth &lt;thuth@redhat.com&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Signed-off-by: David Hildenbrand &lt;david@redhat.com&gt;
Message-Id: &lt;20190225200318.16102-2-david@redhat.com&gt;
Signed-off-by: Cornelia Huck &lt;cohuck@redhat.com&gt;
</content>
</entry>
<entry>
<title>target/s390x: Implement load-on-condition-2 insns</title>
<updated>2017-06-23T16:17:44+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2017-06-16T23:35:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=45aa9aa3b7730b38403553355b36a29f8905916a'/>
<id>urn:sha1:45aa9aa3b7730b38403553355b36a29f8905916a</id>
<content type='text'>
Reviewed-by: Aurelien Jarno &lt;aurelien@aurel32.net&gt;
Signed-off-by: Richard Henderson &lt;rth@twiddle.net&gt;
</content>
</entry>
<entry>
<title>Move target-* CPU file into a target/ folder</title>
<updated>2016-12-20T20:52:12+00:00</updated>
<author>
<name>Thomas Huth</name>
</author>
<published>2016-10-11T06:56:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=fcf5ef2ab52c621a4617ebbef36bf43b4003f4c0'/>
<id>urn:sha1:fcf5ef2ab52c621a4617ebbef36bf43b4003f4c0</id>
<content type='text'>
We've currently got 18 architectures in QEMU, and thus 18 target-xxx
folders in the root folder of the QEMU source tree. More architectures
(e.g. RISC-V, AVR) are likely to be included soon, too, so the main
folder of the QEMU sources slowly gets quite overcrowded with the
target-xxx folders.
To disburden the main folder a little bit, let's move the target-xxx
folders into a dedicated target/ folder, so that target-xxx/ simply
becomes target/xxx/ instead.

Acked-by: Laurent Vivier &lt;laurent@vivier.eu&gt; [m68k part]
Acked-by: Bastian Koppelmann &lt;kbastian@mail.uni-paderborn.de&gt; [tricore part]
Acked-by: Michael Walle &lt;michael@walle.cc&gt; [lm32 part]
Acked-by: Cornelia Huck &lt;cornelia.huck@de.ibm.com&gt; [s390x part]
Reviewed-by: Christian Borntraeger &lt;borntraeger@de.ibm.com&gt; [s390x part]
Acked-by: Eduardo Habkost &lt;ehabkost@redhat.com&gt; [i386 part]
Acked-by: Artyom Tarasenko &lt;atar4qemu@gmail.com&gt; [sparc part]
Acked-by: Richard Henderson &lt;rth@twiddle.net&gt; [alpha part]
Acked-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt; [xtensa part]
Reviewed-by: David Gibson &lt;david@gibson.dropbear.id.au&gt; [ppc part]
Acked-by: Edgar E. Iglesias &lt;edgar.iglesias@xilinx.com&gt; [cris&amp;microblaze part]
Acked-by: Guan Xuetao &lt;gxt@mprc.pku.edu.cn&gt; [unicore32 part]
Signed-off-by: Thomas Huth &lt;thuth@redhat.com&gt;
</content>
</entry>
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