<feed xmlns='http://www.w3.org/2005/Atom'>
<title>bwlp/qemu.git/target/xtensa, branch spice_video_codecs</title>
<subtitle>Experimental fork of QEMU with video encoding patches</subtitle>
<id>https://git.openslx.org/bwlp/qemu.git/atom/target/xtensa?h=spice_video_codecs</id>
<link rel='self' href='https://git.openslx.org/bwlp/qemu.git/atom/target/xtensa?h=spice_video_codecs'/>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/'/>
<updated>2022-10-31T21:31:41+00:00</updated>
<entry>
<title>accel/tcg: Remove will_exit argument from cpu_restore_state</title>
<updated>2022-10-31T21:31:41+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-10-24T13:09:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=3d419a4dd227f174447e0b3978028a1cd52ccc5e'/>
<id>urn:sha1:3d419a4dd227f174447e0b3978028a1cd52ccc5e</id>
<content type='text'>
The value passed is always true, and if the target's
synchronize_from_tb hook is non-trivial, not exiting
may be erroneous.

Reviewed-by: Claudio Fontana &lt;cfontana@suse.de&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>target/xtensa: Convert to tcg_ops restore_state_to_opc</title>
<updated>2022-10-26T01:11:28+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-10-24T11:08:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=044dcfc5aab2f2679148c9eca41441dd6cf276a0'/>
<id>urn:sha1:044dcfc5aab2f2679148c9eca41441dd6cf276a0</id>
<content type='text'>
Reviewed-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>hw/core: Add CPUClass.get_pc</title>
<updated>2022-10-04T19:13:12+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-09-30T17:31:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=e4fdf9df5b1c2aa427de796bea973520027ddd15'/>
<id>urn:sha1:e4fdf9df5b1c2aa427de796bea973520027ddd15</id>
<content type='text'>
Populate this new method for all targets.  Always match
the result that would be given by cpu_get_tb_cpu_state,
as we will want these values to correspond in the logs.

Reviewed-by: Taylor Simpson &lt;tsimpson@quicinc.com&gt;
Reviewed-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Reviewed-by: Mark Cave-Ayland &lt;mark.cave-ayland@ilande.co.uk&gt; (target/sparc)
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
---
Cc: Eduardo Habkost &lt;eduardo@habkost.net&gt; (supporter:Machine core)
Cc: Marcel Apfelbaum &lt;marcel.apfelbaum@gmail.com&gt; (supporter:Machine core)
Cc: "Philippe Mathieu-Daudé" &lt;f4bug@amsat.org&gt; (reviewer:Machine core)
Cc: Yanan Wang &lt;wangyanan55@huawei.com&gt; (reviewer:Machine core)
Cc: Michael Rolnik &lt;mrolnik@gmail.com&gt; (maintainer:AVR TCG CPUs)
Cc: "Edgar E. Iglesias" &lt;edgar.iglesias@gmail.com&gt; (maintainer:CRIS TCG CPUs)
Cc: Taylor Simpson &lt;tsimpson@quicinc.com&gt; (supporter:Hexagon TCG CPUs)
Cc: Song Gao &lt;gaosong@loongson.cn&gt; (maintainer:LoongArch TCG CPUs)
Cc: Xiaojuan Yang &lt;yangxiaojuan@loongson.cn&gt; (maintainer:LoongArch TCG CPUs)
Cc: Laurent Vivier &lt;laurent@vivier.eu&gt; (maintainer:M68K TCG CPUs)
Cc: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt; (reviewer:MIPS TCG CPUs)
Cc: Aleksandar Rikalo &lt;aleksandar.rikalo@syrmia.com&gt; (reviewer:MIPS TCG CPUs)
Cc: Chris Wulff &lt;crwulff@gmail.com&gt; (maintainer:NiosII TCG CPUs)
Cc: Marek Vasut &lt;marex@denx.de&gt; (maintainer:NiosII TCG CPUs)
Cc: Stafford Horne &lt;shorne@gmail.com&gt; (odd fixer:OpenRISC TCG CPUs)
Cc: Yoshinori Sato &lt;ysato@users.sourceforge.jp&gt; (reviewer:RENESAS RX CPUs)
Cc: Mark Cave-Ayland &lt;mark.cave-ayland@ilande.co.uk&gt; (maintainer:SPARC TCG CPUs)
Cc: Bastian Koppelmann &lt;kbastian@mail.uni-paderborn.de&gt; (maintainer:TriCore TCG CPUs)
Cc: Max Filippov &lt;jcmvbkbc@gmail.com&gt; (maintainer:Xtensa TCG CPUs)
Cc: qemu-arm@nongnu.org (open list:ARM TCG CPUs)
Cc: qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs)
Cc: qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs)
Cc: qemu-s390x@nongnu.org (open list:S390 TCG CPUs)
</content>
</entry>
<entry>
<title>target/xtensa: Honour -semihosting-config userspace=on</title>
<updated>2022-09-13T16:18:21+00:00</updated>
<author>
<name>Peter Maydell</name>
</author>
<published>2022-08-22T14:12:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=870ab98bee4312caf0ced42999e295f741aba853'/>
<id>urn:sha1:870ab98bee4312caf0ced42999e295f741aba853</id>
<content type='text'>
Honour the commandline -semihosting-config userspace=on option,
instead of always permitting userspace semihosting calls in system
emulation mode, by passing the correct value to the is_userspace
argument of semihosting_enabled().

Note that this is a behaviour change: if the user wants to
do semihosting calls from userspace they must now specifically
enable them on the command line.

xtensa semihosting is not implemented for linux-user builds.

Signed-off-by: Peter Maydell &lt;peter.maydell@linaro.org&gt;
Acked-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-Id: &lt;20220822141230.3658237-7-peter.maydell@linaro.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>semihosting: Allow optional use of semihosting from userspace</title>
<updated>2022-09-13T16:18:21+00:00</updated>
<author>
<name>Peter Maydell</name>
</author>
<published>2022-08-22T14:12:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=5202861b20d77b1d638da5f10af0f51ebcfc61bf'/>
<id>urn:sha1:5202861b20d77b1d638da5f10af0f51ebcfc61bf</id>
<content type='text'>
Currently our semihosting implementations generally prohibit use of
semihosting calls in system emulation from the guest userspace.  This
is a very long standing behaviour justified originally "to provide
some semblance of security" (since code with access to the
semihosting ABI can do things like read and write arbitrary files on
the host system).  However, it is sometimes useful to be able to run
trusted guest code which performs semihosting calls from guest
userspace, notably for test code.  Add a command line suboption to
the existing semihosting-config option group so that you can
explicitly opt in to semihosting from guest userspace with
 -semihosting-config userspace=on

(There is no equivalent option for the user-mode emulator, because
there by definition all code runs in userspace and has access to
semihosting already.)

This commit adds the infrastructure for the command line option and
adds a bool 'is_user' parameter to the function
semihosting_userspace_enabled() that target code can use to check
whether it should be permitting the semihosting call for userspace.
It mechanically makes all the callsites pass 'false', so they
continue checking "is semihosting enabled in general".  Subsequent
commits will make each target that implements semihosting honour the
userspace=on option by passing the correct value and removing
whatever "don't do this for userspace" checking they were doing by
hand.

Signed-off-by: Peter Maydell &lt;peter.maydell@linaro.org&gt;
Acked-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Reviewed-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-Id: &lt;20220822141230.3658237-2-peter.maydell@linaro.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>accel/tcg: Add pc and host_pc params to gen_intermediate_code</title>
<updated>2022-09-06T07:04:26+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-08-11T20:48:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=306c872103b4d0986c9f671eb7538b0b70bf69b5'/>
<id>urn:sha1:306c872103b4d0986c9f671eb7538b0b70bf69b5</id>
<content type='text'>
Pass these along to translator_loop -- pc may be used instead
of tb-&gt;pc, and host_pc is currently unused.  Adjust all targets
at one time.

Acked-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
Acked-by: Ilya Leoshkevich &lt;iii@linux.ibm.com&gt;
Tested-by: Ilya Leoshkevich &lt;iii@linux.ibm.com&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>Clean up decorations and whitespace around header guards</title>
<updated>2022-05-11T14:50:32+00:00</updated>
<author>
<name>Markus Armbruster</name>
</author>
<published>2022-05-06T13:49:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=ea9cea93c69d508a333dd1b0cb1a44f6daf80b63'/>
<id>urn:sha1:ea9cea93c69d508a333dd1b0cb1a44f6daf80b63</id>
<content type='text'>
Cleaned up with scripts/clean-header-guards.pl.

Signed-off-by: Markus Armbruster &lt;armbru@redhat.com&gt;
Message-Id: &lt;20220506134911.2856099-5-armbru@redhat.com&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>Normalize header guard symbol definition</title>
<updated>2022-05-11T14:50:26+00:00</updated>
<author>
<name>Markus Armbruster</name>
</author>
<published>2022-05-06T13:49:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=4f31b54bfe52c72be9c17c158b38924e6cefcd0f'/>
<id>urn:sha1:4f31b54bfe52c72be9c17c158b38924e6cefcd0f</id>
<content type='text'>
We commonly define the header guard symbol without an explicit value.
Normalize the exceptions.

Done with scripts/clean-header-guards.pl.

Signed-off-by: Markus Armbruster &lt;armbru@redhat.com&gt;
Message-Id: &lt;20220506134911.2856099-4-armbru@redhat.com&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>Clean up header guards that don't match their file name</title>
<updated>2022-05-11T14:49:06+00:00</updated>
<author>
<name>Markus Armbruster</name>
</author>
<published>2022-05-06T13:49:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=52581c718c5cd55595ca032a56f1e194c5716456'/>
<id>urn:sha1:52581c718c5cd55595ca032a56f1e194c5716456</id>
<content type='text'>
Header guard symbols should match their file name to make guard
collisions less likely.

Cleaned up with scripts/clean-header-guards.pl, followed by some
renaming of new guard symbols picked by the script to better ones.

Signed-off-by: Markus Armbruster &lt;armbru@redhat.com&gt;
Message-Id: &lt;20220506134911.2856099-2-armbru@redhat.com&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
[Change to generated file ebpf/rss.bpf.skeleton.h backed out]
</content>
</entry>
<entry>
<title>target/xtensa: implement cache test option opcodes</title>
<updated>2022-05-06T22:37:10+00:00</updated>
<author>
<name>Max Filippov</name>
</author>
<published>2022-05-02T05:57:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=59491e97f89eaeee275f57fb6bb40f0152429fb3'/>
<id>urn:sha1:59491e97f89eaeee275f57fb6bb40f0152429fb3</id>
<content type='text'>
We don't model caches, so for l*ct opcodes return tags with all bits
(including Valid) set to 0. For all other opcodes don't do anything.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
</feed>
