bwlp/qemu.git/tcg/arm, branch master

Replace config-time define HOST_WORDS_BIGENDIAN

2022-04-06T08:50:37+00:00

Replace a config-time define with a compile time condition define (compatible with clang and gcc) that must be declared prior to its usage. This avoids having a global configure time define, but also prevents from bad usage, if the config header wasn't included before. This can help to make some code independent from qemu too. gcc supports __BYTE_ORDER__ from about 4.6 and clang from 3.2. Signed-off-by: Marc-André Lureau [ For the s390x parts I'm involved in ] Acked-by: Halil Pasic Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20220323155743.1585078-7-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini

tcg/arm: Don't emit UNPREDICTABLE LDRD with Rm == Rt or Rt+1

2022-03-14T17:31:51+00:00

The LDRD (register) instruction is UNPREDICTABLE if the Rm register is the same as either Rt or Rt+1 (the two registers being loaded to). We weren't making sure we avoided this, with the result that on some host CPUs like the Cortex-A7 we would get a SIGILL because the CPU chooses to UNDEF for this particular UNPREDICTABLE case. Since we've already checked that datalo is aligned, we can simplify the test vs the Rm operand by aligning it before comparison. Check for the two orderings before falling back to two ldr instructions. We don't bother to do anything similar for tcg_out_ldrd_rwb(), because it is only used in tcg_out_tlb_read() with a fixed set of registers which don't overlap. There is no equivalent UNPREDICTABLE case for STRD. Reviewed-by: Alex Bennée Resolves: https://gitlab.com/qemu-project/qemu/-/issues/896 Signed-off-by: Richard Henderson

tcg: Add opcodes for vector nand, nor, eqv

2022-03-04T18:50:41+00:00

We've had placeholders for these opcodes for a while, and should have support on ppc, s390x and avx512 hosts. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson

tcg/arm: Support raising sigbus for user-only

2022-02-08T21:55:02+00:00

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson

tcg/arm: Reserve a register for guest_base

2022-02-08T21:55:02+00:00

Reserve a register for the guest_base using aarch64 for reference. By doing so, we do not have to recompute it for every memory load. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson

tcg/arm: Support unaligned access for softmmu

2022-02-08T21:55:02+00:00

From armv6, the architecture supports unaligned accesses. All we need to do is perform the correct alignment check in tcg_out_tlb_read. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson

tcg/arm: Check alignment for ldrd and strd

2022-02-08T21:55:02+00:00

We will shortly allow the use of unaligned memory accesses, and these require proper alignment. Use get_alignment_bits to verify and remove USING_SOFTMMU. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson

tcg/arm: Remove use_armv6_instructions

2022-02-08T21:55:02+00:00

This is now always true, since we require armv6. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson

tcg/arm: Remove use_armv5t_instructions

2022-02-08T21:55:02+00:00

This is now always true, since we require armv6. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson

tcg/arm: Drop support for armv4 and armv5 hosts

2022-02-08T21:55:02+00:00

Support for unaligned accesses is difficult for pre-v6 hosts. While debian still builds for armv4, we cannot use a compile time test, so test the architecture at runtime and error out. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson