Experimental fork of QEMU with video encoding patches https://git.openslx.org/bwlp/qemu.git/atom/tcg/i386/tcg-target.opc.h?h=spice_video_codecs 2022-03-04T18:50:41+00:00 2022-03-04T18:50:41+00:00 Richard Henderson 2021-12-18T18:48:43+00:00 urn:sha1:965d5d0681a99540bf19f313a66ecb14cee2654a We will use VPSHLD, VPSHLDV and VPSHRDV for 16-bit rotates. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2019-11-11T14:11:21+00:00 Peter Maydell 2019-10-25T15:58:46+00:00 urn:sha1:2029bf7e525e15a7e5f1ea4e2bee29224bf60ee3 Add the copyright/license boilerplate for tcg/i386/tcg-target.opc.h. This file has had only one commit, 770c2fc7bb70804a, by a Linaro engineer. The license is MIT, since that's what the rest of tcg/i386/ is. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20191025155848.17362-3-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2018-02-08T15:54:08+00:00 Richard Henderson 2017-08-17T21:47:43+00:00 urn:sha1:770c2fc7bb70804ae9869995fd02dadd6d7656ac The x86 vector instruction set is extremely irregular. With newer editions, Intel has filled in some of the blanks. However, we don't get many 64-bit operations until SSE4.2, introduced in 2009. The subsequent edition was for AVX1, introduced in 2011, which added three-operand addressing, and adjusts how all instructions should be encoded. Given the relatively narrow 2 year window between possible to support and desirable to support, and to vastly simplify code maintainence, I am only planning to support AVX1 and later cpus. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>