Experimental fork of QEMU with video encoding patches https://git.openslx.org/bwlp/qemu.git/atom/tcg/i386?h=spice_video_codecs 2022-08-01T09:58:02+00:00 2022-08-01T09:58:02+00:00 Daniel P. Berrangé 2022-07-07T16:37:15+00:00 urn:sha1:7a21bee2aa52fc95b25e38372678986ee94f05f1 Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20220707163720.1421716-5-berrange@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com> 2022-06-02T15:09:46+00:00 Richard Henderson 2022-06-01T23:22:19+00:00 urn:sha1:3cc18d18cc3865d7b1ce2c8b35d52e52abbff397 We wanted the VPSRAQ variant with the scalar vector shift operand, not the variant with an immediate operand. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1022 Fixes: 47b331b2a8da ("tcg/i386: Implement avx512 scalar shift") Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2022-03-04T18:50:41+00:00 Richard Henderson 2021-12-16T16:06:33+00:00 urn:sha1:cf320769476c3e2820be2a6280bfa1e15baf396f The general ternary logic operation can implement BITSEL. Funnel the 4-operand operation into three variants of the 3-operand instruction, depending on input operand overlap. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2022-03-04T18:50:41+00:00 Richard Henderson 2021-12-16T15:37:02+00:00 urn:sha1:3143767b743b3512a056d4d8ecdc104a95334a37 AVX512VL has a general ternary logic operation, VPTERNLOGQ, which can implement NOT, ORC, NAND, NOR, EQV. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2022-03-04T18:50:41+00:00 Richard Henderson 2021-12-16T15:14:24+00:00 urn:sha1:4c8b9686833f595176d28a90c973e0e469c7ebe7 AVX512DQ has VPMULLQ. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2022-03-04T18:50:41+00:00 Richard Henderson 2021-12-16T14:54:26+00:00 urn:sha1:dac1648fd8460fbe0ff219eb41c9940617f28da0 AVX512VL has VPABSQ, VPMAXSQ, VPMAXUQ, VPMINSQ, VPMINUQ. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2022-03-04T18:50:41+00:00 Richard Henderson 2021-12-18T19:25:58+00:00 urn:sha1:1d442e427a66ed90ce3efb0048ceec0f9192cb02 Expand 32-bit and 64-bit scalar rotate with VPRO[LR]V; expand 16-bit scalar rotate with VPSHLDV. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2022-03-04T18:50:41+00:00 Richard Henderson 2021-12-18T19:23:09+00:00 urn:sha1:a2a19b429b0daaf560e03aaa4851feb9f1fc5fac There is no such instruction on x86, so we should not be pretending it has arguments. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2022-03-04T18:50:41+00:00 Richard Henderson 2021-12-18T19:04:34+00:00 urn:sha1:786c7ef3b7668f232b3fe31a6867a7c4d114780e While there are no specific 16-bit rotate instructions, there are double-word shifts, which can perform the same operation. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2022-03-04T18:50:41+00:00 Richard Henderson 2021-12-18T18:48:43+00:00 urn:sha1:965d5d0681a99540bf19f313a66ecb14cee2654a We will use VPSHLD, VPSHLDV and VPSHRDV for 16-bit rotates. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>