<feed xmlns='http://www.w3.org/2005/Atom'>
<title>bwlp/qemu.git/tcg/ppc, branch spice_video_codecs</title>
<subtitle>Experimental fork of QEMU with video encoding patches</subtitle>
<id>https://git.openslx.org/bwlp/qemu.git/atom/tcg/ppc?h=spice_video_codecs</id>
<link rel='self' href='https://git.openslx.org/bwlp/qemu.git/atom/tcg/ppc?h=spice_video_codecs'/>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/'/>
<updated>2022-10-04T19:13:22+00:00</updated>
<entry>
<title>tcg/ppc: Optimize 26-bit jumps</title>
<updated>2022-10-04T19:13:22+00:00</updated>
<author>
<name>Leandro Lupori</name>
</author>
<published>2022-09-19T17:56:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=20add588296a8a24374004e9dbf6219f28665d34'/>
<id>urn:sha1:20add588296a8a24374004e9dbf6219f28665d34</id>
<content type='text'>
PowerPC64 processors handle direct branches better than indirect
ones, resulting in less stalled cycles and branch misses.

However, PPC's tb_target_set_jmp_target() was only using direct
branches for 16-bit jumps, while PowerPC64's unconditional branch
instructions are able to handle displacements of up to 26 bits.
To take advantage of this, now jumps whose displacements fit in
between 17 and 26 bits are also converted to direct branches.

Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Signed-off-by: Leandro Lupori &lt;leandro.lupori@eldorado.org.br&gt;
[rth: Expanded some commentary.]
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>tcg/ppc: implement rem[u]_i{32,64} with mod[su][wd]</title>
<updated>2022-06-20T19:56:28+00:00</updated>
<author>
<name>Matheus Kowalczuk Ferst</name>
</author>
<published>2022-06-13T14:43:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=4d5738222ff0a7f4d56fd4a2971b0605726a8fb2'/>
<id>urn:sha1:4d5738222ff0a7f4d56fd4a2971b0605726a8fb2</id>
<content type='text'>
Power ISA v3.0 introduced mod[su][wd] insns that can be used to
implement rem[u]_i{32,64}.

Signed-off-by: Matheus Ferst &lt;matheus.ferst@eldorado.org.br&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>tcg/ppc: Optimize memory ordering generation with lwsync</title>
<updated>2022-05-26T20:11:33+00:00</updated>
<author>
<name>Nicholas Piggin</name>
</author>
<published>2022-05-19T13:59:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=fc879703f74851e3e861894a0c4a6902877d0c2c'/>
<id>urn:sha1:fc879703f74851e3e861894a0c4a6902877d0c2c</id>
<content type='text'>
lwsync orders more than just LD_LD, importantly it matches x86 and
s390 default memory ordering.

Signed-off-by: Nicholas Piggin &lt;npiggin@gmail.com&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-Id: &lt;20220519135908.21282-4-npiggin@gmail.com&gt;
Signed-off-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
</content>
</entry>
<entry>
<title>tcg/ppc: ST_ST memory ordering is not provided with eieio</title>
<updated>2022-05-26T20:11:33+00:00</updated>
<author>
<name>Nicholas Piggin</name>
</author>
<published>2022-05-19T13:59:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=9d82353826422ed0e34ad76961fe0cae5f67e58e'/>
<id>urn:sha1:9d82353826422ed0e34ad76961fe0cae5f67e58e</id>
<content type='text'>
eieio does not provide ordering between stores to CI memory and stores
to cacheable memory so it can't be used as a general ST_ST barrier.

Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Signed-of-by: Nicholas Piggin &lt;npiggin@gmail.com&gt;
Message-Id: &lt;20220519135908.21282-3-npiggin@gmail.com&gt;
Signed-off-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
</content>
</entry>
<entry>
<title>target/ppc: declare vmsumuh[ms] helper with call flags</title>
<updated>2022-05-26T20:11:33+00:00</updated>
<author>
<name>Matheus Ferst</name>
</author>
<published>2022-05-17T12:39:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=89a5a1aee2df29c311d11386923b750bf1ea6bc2'/>
<id>urn:sha1:89a5a1aee2df29c311d11386923b750bf1ea6bc2</id>
<content type='text'>
Move vmsumuhm and vmsumuhs to decodetree, declare vmsumuhm helper with
TCG_CALL_NO_RWG, and drop the unused env argument.

Signed-off-by: Matheus Ferst &lt;matheus.ferst@eldorado.org.br&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-Id: &lt;20220517123929.284511-12-matheus.ferst@eldorado.org.br&gt;
[danielhb: added #undef VMSUMUHM to fix ppc64 build]
Signed-off-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
</content>
</entry>
<entry>
<title>Replace config-time define HOST_WORDS_BIGENDIAN</title>
<updated>2022-04-06T08:50:37+00:00</updated>
<author>
<name>Marc-André Lureau</name>
</author>
<published>2022-03-23T15:57:17+00:00</published>
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<id>urn:sha1:e03b56863d2bca3e649e81531c1b0299524481ae</id>
<content type='text'>
Replace a config-time define with a compile time condition
define (compatible with clang and gcc) that must be declared prior to
its usage. This avoids having a global configure time define, but also
prevents from bad usage, if the config header wasn't included before.

This can help to make some code independent from qemu too.

gcc supports __BYTE_ORDER__ from about 4.6 and clang from 3.2.

Signed-off-by: Marc-André Lureau &lt;marcandre.lureau@redhat.com&gt;
[ For the s390x parts I'm involved in ]
Acked-by: Halil Pasic &lt;pasic@linux.ibm.com&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-Id: &lt;20220323155743.1585078-7-marcandre.lureau@redhat.com&gt;
Signed-off-by: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
</content>
</entry>
<entry>
<title>tcg/ppc: Implement vector NAND, NOR, EQV</title>
<updated>2022-03-04T18:50:41+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2021-12-18T02:52:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=fa8e90d69f94d3d54369d763200691ba8f1c1751'/>
<id>urn:sha1:fa8e90d69f94d3d54369d763200691ba8f1c1751</id>
<content type='text'>
Tested-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Reviewed-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>tcg: Add opcodes for vector nand, nor, eqv</title>
<updated>2022-03-04T18:50:41+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2021-12-16T19:17:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=ed5234735af0c9ddc120ba2297e47714c5126abd'/>
<id>urn:sha1:ed5234735af0c9ddc120ba2297e47714c5126abd</id>
<content type='text'>
We've had placeholders for these opcodes for a while,
and should have support on ppc, s390x and avx512 hosts.

Tested-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Reviewed-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>target/ppc: moved vector even and odd multiplication to decodetree</title>
<updated>2022-03-02T05:51:36+00:00</updated>
<author>
<name>Lucas Mateus Castro (alqotel)</name>
</author>
<published>2022-03-02T05:51:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=80eca687c8513a7e1611e0441abdd68b0c02a1d6'/>
<id>urn:sha1:80eca687c8513a7e1611e0441abdd68b0c02a1d6</id>
<content type='text'>
Moved the instructions vmulesb, vmulosb, vmuleub, vmuloub,
vmulesh, vmulosh, vmuleuh, vmulouh, vmulesw, vmulosw,
muleuw and vmulouw from legacy to decodetree. Implemented
the instructions vmulesd, vmulosd, vmuleud, vmuloud.

Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Signed-off-by: Lucas Mateus Castro (alqotel) &lt;lucas.araujo@eldorado.org.br&gt;
Signed-off-by: Matheus Ferst &lt;matheus.ferst@eldorado.org.br&gt;
Message-Id: &lt;20220225210936.1749575-3-matheus.ferst@eldorado.org.br&gt;
Signed-off-by: Cédric Le Goater &lt;clg@kaod.org&gt;
</content>
</entry>
<entry>
<title>tcg/ppc: Support raising sigbus for user-only</title>
<updated>2022-02-08T21:55:02+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2021-08-03T22:08:55+00:00</published>
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<id>urn:sha1:8605cbcdeedb5f24a20dd1341a7a08bd9f38be71</id>
<content type='text'>
Reviewed-by: Peter Maydell &lt;peter.maydell@linaro.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
</feed>
