Experimental fork of QEMU with video encoding patches https://git.openslx.org/bwlp/qemu.git/atom/tcg/sparc?h=master 2022-10-31T20:28:53+00:00 2022-10-31T20:28:53+00:00 Richard Henderson 2022-10-17T05:00:57+00:00 urn:sha1:6d0b52ed889f47fa8e39e9611d7bce15cc533369 Emphasize that we only support full 64-bit code generation. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2022-10-31T20:28:53+00:00 Richard Henderson 2022-10-17T04:28:30+00:00 urn:sha1:3a5f6805c7ca7deb8d1abaf0153936eeb51d074e Since 9b9c37c36439, we have only supported sparc64 cpus. Debian and Gentoo now only support 64-bit sparc64 userland, so it is time to drop the 32-bit sparc64 userland: sparc32plus. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2022-02-08T22:00:00+00:00 Richard Henderson 2021-08-05T00:54:30+00:00 urn:sha1:321dbde33a6aa8e7780a3b6b4746628d215a1fec This is kinda sorta the opposite of the other tcg hosts, where we get (normal) alignment checks for free with host SIGBUS and need to add code to support unaligned accesses. This inline code expansion is somewhat large, but it takes quite a few instructions to make a function call to a helper anyway. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2022-02-08T22:00:00+00:00 Richard Henderson 2021-08-04T23:23:05+00:00 urn:sha1:e01d60f211251388a5d9ae7e02d0b4500af26966 Due to mapping changes, we now rarely place the code_gen_buffer near the main executable. Which means that direct calls will now rarely be in range. So, always use indirect calls for tail calls, which allows us to avoid clobbering %o7, and therefore we need not save and restore it. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2022-02-08T22:00:00+00:00 Richard Henderson 2021-08-05T01:34:20+00:00 urn:sha1:c834b8d81b0ee597d185a4d8127dfc76230307c8 Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2022-02-08T21:59:06+00:00 Richard Henderson 2022-02-05T05:12:30+00:00 urn:sha1:6a6bfa3c60ba70e870f8355b9d3508915c90c13a Since 7ecd02a06f8, if patch_reloc fails we restart translation with a smaller TB. SPARC had its function signature changed, but not the logic. Replace assert with return false. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2022-02-08T21:59:06+00:00 Richard Henderson 2021-08-05T01:09:15+00:00 urn:sha1:684db2a0b04ff024d0a275de85982fe5892185d3 We had code for checking for 13 and 21-bit shifted constants, but we can do better and allow 32-bit shifted constants. This is still 2 insns shorter than the full 64-bit sequence. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2022-02-08T21:58:44+00:00 Richard Henderson 2021-08-04T23:16:05+00:00 urn:sha1:92840d06faeed2038b90d5b168c18d73ca3a44b8 This will allow us to control exactly what scratch register is used for loading the constant. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2022-02-08T21:57:42+00:00 Richard Henderson 2022-02-07T23:46:40+00:00 urn:sha1:c71929c345d08fa70edb1eeaa9babaaf5d6a9bf7 Handle 32-bit constants with a separate function, so that tcg_out_movi_int does not need to recurse. This slightly rearranges the order of tests for small constants, but produces the same output. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2022-02-08T21:56:50+00:00 Richard Henderson 2022-02-07T23:15:58+00:00 urn:sha1:414399b6b8a02f03d3b0cba5cfa9205dff618a9b When BH is constant, it is constrained to 11 bits for use in MOVCC. For the cases in which we must load the constant BH into a register, we do not need the full logic of tcg_out_movi; we can use the simpler function for emitting a 13 bit constant. This eliminates the only case in which TCG_REG_T2 was passed to tcg_out_movi, which will shortly become invalid. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>