<feed xmlns='http://www.w3.org/2005/Atom'>
<title>bwlp/qemu.git/tcg, branch spice_video_codecs</title>
<subtitle>Experimental fork of QEMU with video encoding patches</subtitle>
<id>https://git.openslx.org/bwlp/qemu.git/atom/tcg?h=spice_video_codecs</id>
<link rel='self' href='https://git.openslx.org/bwlp/qemu.git/atom/tcg?h=spice_video_codecs'/>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/'/>
<updated>2022-11-09T01:29:03+00:00</updated>
<entry>
<title>tcg: Move TCG_TARGET_HAS_direct_jump init to tb_gen_code</title>
<updated>2022-11-09T01:29:03+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-11-05T23:55:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=35abb009b22e93e89cc627de74fa90339b680882'/>
<id>urn:sha1:35abb009b22e93e89cc627de74fa90339b680882</id>
<content type='text'>
Reviewed-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'pull-testing-for-7.2-011122-3' of https://github.com/stsquad/qemu into staging</title>
<updated>2022-11-01T17:39:06+00:00</updated>
<author>
<name>Stefan Hajnoczi</name>
</author>
<published>2022-11-01T17:39:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=0d37413c639d8f467fc92c86a1ed54ecdba5220d'/>
<id>urn:sha1:0d37413c639d8f467fc92c86a1ed54ecdba5220d</id>
<content type='text'>
testing and plugin updates for 7.2:

  - cleanup win32/64 docker files
  - update test-mingw test
  - add flex/bison to debian-all-test
  - handle --enable-static/--disable-pie in config
  - extend timeouts on x86_64 avocado tests
  - add flex/bison to debian-hexagon-cross
  - use regular semihosting for nios2 check-tcg
  - fix obscure linker error to nios2 softmmu tests
  - various windows portability fixes for tests
  - clean-up of MAINTAINERS
  - use -machine none when appropriate in avocado
  - make raspi2_initrd test detect shutdown
  - disable sh4 rd2 tests on gitlab
  - re-enable threadcount/linux-test for sh4
  - clean-up s390x handling of "ex" instruction
  - better handle new CPUs in execlog plugin
  - pass CONFIG_DEBUG_TCG to plugin builds
  - try and avoid races in test-io-channel-command
  - speed up ssh key checking for tests/vm

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# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 01 Nov 2022 09:49:39 EDT
# gpg:                using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) &lt;alex.bennee@linaro.org&gt;" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8  DF35 FBD0 DB09 5A9E 2A44

* tag 'pull-testing-for-7.2-011122-3' of https://github.com/stsquad/qemu: (31 commits)
  tests/vm: use -o IdentitiesOnly=yes for ssh
  tests/unit: cleanups for test-io-channel-command
  contrib/plugins: protect execlog's last_exec expansion
  contrib/plugins: enable debug on CONFIG_DEBUG_TCG
  tests/tcg: include CONFIG_PLUGIN in config-host.mak
  target/s390x: fake instruction loading when handling 'ex'
  target/s390x: don't probe next pc for EXecuted insns
  target/s390x: don't use ld_code2 to probe next pc
  tests/tcg: re-enable threadcount for sh4
  tests/tcg: re-enable linux-test for sh4
  tests/avocado: disable sh4 rd2 tests on Gitlab
  tests/avocado: raspi2_initrd: Wait for guest shutdown message before stopping
  tests/avocado: set -machine none for userfwd and vnc tests
  MAINTAINERS: fix-up for check-tcg Makefile changes
  MAINTAINERS: add features_to_c.sh to gdbstub files
  MAINTAINERS: add entries for the key build bits
  hw/usb: dev-mtp: Use g_mkdir()
  block/vvfat: Unify the mkdir() call
  tcg: Avoid using hardcoded /tmp
  semihosting/arm-compat-semi: Avoid using hardcoded /tmp
  ...

Signed-off-by: Stefan Hajnoczi &lt;stefanha@redhat.com&gt;
</content>
</entry>
<entry>
<title>tcg: Avoid using hardcoded /tmp</title>
<updated>2022-10-31T20:37:58+00:00</updated>
<author>
<name>Bin Meng</name>
</author>
<published>2022-10-27T18:36:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=eb6b2edf8e1a5845c81f3c4da905f1f8bbc0dec3'/>
<id>urn:sha1:eb6b2edf8e1a5845c81f3c4da905f1f8bbc0dec3</id>
<content type='text'>
Use g_get_tmp_dir() to get the directory to use for temporary files.

Signed-off-by: Bin Meng &lt;bin.meng@windriver.com&gt;
Reviewed-by: Marc-André Lureau &lt;marcandre.lureau@redhat.com&gt;
Reviewed-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Signed-off-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
Message-Id: &lt;20221006151927.2079583-3-bmeng.cn@gmail.com&gt;
Message-Id: &lt;20221027183637.2772968-12-alex.bennee@linaro.org&gt;
</content>
</entry>
<entry>
<title>tcg/tci: fix logic error when registering helpers via FFI</title>
<updated>2022-10-31T20:28:53+00:00</updated>
<author>
<name>Icenowy Zheng</name>
</author>
<published>2022-10-28T19:23:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=9dd1d56e570e5119fef2b28fda811d6891e597a8'/>
<id>urn:sha1:9dd1d56e570e5119fef2b28fda811d6891e597a8</id>
<content type='text'>
When registering helpers via FFI for TCI, the inner loop that iterates
parameters of the helper reuses (and thus pollutes) the same variable
used by the outer loop that iterates all helpers, thus made some helpers
unregistered.

Fix this logic error by using a dedicated temporary variable for the
inner loop.

Fixes: 22f15579fa ("tcg: Build ffi data structures for helpers")
Reviewed-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
Signed-off-by: Icenowy Zheng &lt;uwu@icenowy.me&gt;
Message-Id: &lt;20221028072145.1593205-1-uwu@icenowy.me&gt;
[rth: Move declaration of j to the for loop itself]
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>tcg/sparc64: Remove sparc32plus constraints</title>
<updated>2022-10-31T20:28:53+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-10-17T05:17:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=a59a293126604183dd63bf8b890393e32e7702c4'/>
<id>urn:sha1:a59a293126604183dd63bf8b890393e32e7702c4</id>
<content type='text'>
With sparc64 we need not distinguish between registers that
can hold 32-bit values and those that can hold 64-bit values.

Reviewed-by: Peter Maydell &lt;peter.maydell@linaro.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>tcg/sparc64: Rename from tcg/sparc</title>
<updated>2022-10-31T20:28:53+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-10-17T05:00:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=6d0b52ed889f47fa8e39e9611d7bce15cc533369'/>
<id>urn:sha1:6d0b52ed889f47fa8e39e9611d7bce15cc533369</id>
<content type='text'>
Emphasize that we only support full 64-bit code generation.

Reviewed-by: Peter Maydell &lt;peter.maydell@linaro.org&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>tcg/sparc: Remove support for sparc32plus</title>
<updated>2022-10-31T20:28:53+00:00</updated>
<author>
<name>Richard Henderson</name>
</author>
<published>2022-10-17T04:28:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=3a5f6805c7ca7deb8d1abaf0153936eeb51d074e'/>
<id>urn:sha1:3a5f6805c7ca7deb8d1abaf0153936eeb51d074e</id>
<content type='text'>
Since 9b9c37c36439, we have only supported sparc64 cpus.
Debian and Gentoo now only support 64-bit sparc64 userland,
so it is time to drop the 32-bit sparc64 userland: sparc32plus.

Reviewed-by: Peter Maydell &lt;peter.maydell@linaro.org&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>tcg/aarch64: Remove unused code in tcg_out_op</title>
<updated>2022-10-25T12:01:14+00:00</updated>
<author>
<name>Qi Hu</name>
</author>
<published>2022-10-17T02:08:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=122167659c50958f98cb2a153de97541f03462ff'/>
<id>urn:sha1:122167659c50958f98cb2a153de97541f03462ff</id>
<content type='text'>
AArch64 defines the TCG_TARGET_HAS_direct_jump. So the "else" block is
useless in the case of "INDEX_op_goto_tb" in function "tcg_out_op". Add
an assertion and delete these codes for clarity.

Suggested-by: WANG Xuerui &lt;git@xen0n.name&gt;
Signed-off-by: Qi Hu &lt;huqi@loongson.cn&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-Id: &lt;20221017020826.990729-1-huqi@loongson.cn&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>tcg/loongarch64: Add direct jump support</title>
<updated>2022-10-25T12:01:14+00:00</updated>
<author>
<name>Qi Hu</name>
</author>
<published>2022-10-15T09:27:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=f072a1ae7fb47db75eb3c6b960759c908884f585'/>
<id>urn:sha1:f072a1ae7fb47db75eb3c6b960759c908884f585</id>
<content type='text'>
Similar to the ARM64, LoongArch has PC-relative instructions such as
PCADDU18I. These instructions can be used to support direct jump for
LoongArch. Additionally, if instruction "B offset" can cover the target
address(target is within ±128MB range), a single "B offset" plus a nop
will be used by "tb_target_set_jump_target".

Signed-off-by: Qi Hu &lt;huqi@loongson.cn&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Reviewed-by: WANG Xuerui &lt;git@xen0n.name&gt;
Message-Id: &lt;20221015092754.91971-1-huqi@loongson.cn&gt;
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
<entry>
<title>tcg/ppc: Optimize 26-bit jumps</title>
<updated>2022-10-04T19:13:22+00:00</updated>
<author>
<name>Leandro Lupori</name>
</author>
<published>2022-09-19T17:56:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=20add588296a8a24374004e9dbf6219f28665d34'/>
<id>urn:sha1:20add588296a8a24374004e9dbf6219f28665d34</id>
<content type='text'>
PowerPC64 processors handle direct branches better than indirect
ones, resulting in less stalled cycles and branch misses.

However, PPC's tb_target_set_jmp_target() was only using direct
branches for 16-bit jumps, while PowerPC64's unconditional branch
instructions are able to handle displacements of up to 26 bits.
To take advantage of this, now jumps whose displacements fit in
between 17 and 26 bits are also converted to direct branches.

Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Signed-off-by: Leandro Lupori &lt;leandro.lupori@eldorado.org.br&gt;
[rth: Expanded some commentary.]
Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
</content>
</entry>
</feed>
