Experimental fork of QEMU with video encoding patches https://git.openslx.org/bwlp/qemu.git/atom/tests/tcg/hexagon?h=spice_video_codecs 2022-09-19T18:55:23+00:00 2022-09-19T18:55:23+00:00 Matheus Tavares Bernardino 2022-09-16T15:06:27+00:00 urn:sha1:8888ee42af726b9aba8245022fd4b7350a12acd3 Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Taylor Simpson <tsimpson@quicinc.com> 2022-07-31T23:22:09+00:00 Taylor Simpson 2022-07-18T23:03:20+00:00 urn:sha1:7eabb050ea77e529f549ea1ddaaa18e91ae01e34 The test is in tests/tcg/multiarch/float_convd.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220718230320.24444-4-tsimpson@quicinc.com> 2022-07-31T23:22:09+00:00 Taylor Simpson 2022-07-18T23:03:19+00:00 urn:sha1:a1ad040dbaa7528d4d47a98f2b068015d2da0fcc The increment used in :brev tests was causing unaligned addresses Change the increment and the relevant expected values Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220718230320.24444-3-tsimpson@quicinc.com> 2022-07-31T23:22:09+00:00 Taylor Simpson 2022-07-18T23:03:18+00:00 urn:sha1:1e814a0dc4b255a58f2cdab54aee50b25af2a006 VyV operand is only used in the vshuff and vdeal instructions. These instructions write to both VyV and VxV operands. In the case where both operands are the same register, we need a separate location for VyV. We use the existing vtmp field in CPUHexagonState. Test case added in tests/tcg/hexagon/hvx_misc.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220718230320.24444-2-tsimpson@quicinc.com> 2022-07-19T21:20:08+00:00 Taylor Simpson 2022-07-07T21:05:46+00:00 urn:sha1:15fc6badbd28a126346f84c1acae48e273b66b67 The semantics of a mem_noshuf packet are that the store effectively happens before the load. However, in cases where the load raises an exception, we cannot simply execute the store first. This change adds a probe to check that the load will not raise an exception before executing the store. If the load is predicated, this requires special handling. We check the condition before performing the probe. Since, we need the EA to perform the check, we move the GET_EA portion inside CHECK_NOSHUF_PRED. Test case added in tests/tcg/hexagon/mem_noshuf_exception.c Suggested-by: Alessandro Di Federico <ale@rev.ng> Suggested-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220707210546.15985-3-tsimpson@quicinc.com> 2022-07-19T21:20:08+00:00 Taylor Simpson 2022-07-07T21:05:45+00:00 urn:sha1:cab86dea1d205f5224770de294cc718be467ccf8 Call the CHECK_NOSHUF macro multiple times: once in the fGEN_TCG_PRED_LOAD() and again in fLOAD(). Before this commit, a packet with a store and a predicated load with mem_noshuf that gets encoded like this: { P0 = cmp.eq(R17,#0x0) memw(R18+#0x0) = R2 if (!P0.new) R3 = memw(R17+#0x4) } ... would end up generating a branch over both the load and the store like so: ... brcond_i32 loc17,$0x0,eq,$L1 mov_i32 loc18,store_addr_1 qemu_st_i32 store_val32_1,store_addr_1,leul,0 qemu_ld_i32 loc16,loc7,leul,0 set_label $L1 ... Test cases added to tests/tcg/hexagon/mem_noshuf.c Co-authored-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Brian Cain <bcain@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220707210546.15985-2-tsimpson@quicinc.com> 2022-03-12T17:14:22+00:00 Taylor Simpson 2022-02-10T02:15:56+00:00 urn:sha1:c0d86060f033fc8d591b0163e380ff6cd04f213a On Hexagon, c4 is an alias for predicate registers P3:0. If we assign to c4 inside a packet with reads from predicate registers, the predicate reads should get the old values. Test case added to tests/tcg/hexagon/preg_alias.c Co-authored-by: Michael Lambert <mlambert@cuicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-13-tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> 2022-03-12T17:14:22+00:00 Taylor Simpson 2022-02-10T02:15:54+00:00 urn:sha1:3977ba3078503fca0f182aa8a39fad2388f43cb1 Fix typo that checked for 32 bit nan instead of 64 bit Test case added in tests/tcg/hexagon/usr.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-11-tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> 2022-03-12T17:14:22+00:00 Taylor Simpson 2022-02-10T02:15:53+00:00 urn:sha1:8af2d9978ad2c52377fe69466a556fffeedcd057 Replace consecutive inline asm blocks with a single one with proper outputs/inputs/clobbers rather than making assumptions about register values being carried between separate blocks. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-10-tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> 2022-03-12T17:14:22+00:00 Taylor Simpson 2022-02-10T02:15:52+00:00 urn:sha1:8576e7ecae056845de6e0bafc547501f2bc6461c Add a test that sets USR multiple times in a packet Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-9-tsimpson@quicinc.com> Acked-by: Richard Henderson <richard.henderson@linaro.org>