Experimental fork of QEMU with video encoding patches https://git.openslx.org/bwlp/qemu.git/atom/tests/tcg/i386?h=spice_video_codecs 2022-10-22T07:05:54+00:00 2022-10-22T07:05:54+00:00 Paolo Bonzini 2022-10-19T11:22:06+00:00 urn:sha1:2872b0f390c3fbd8f19f6b82da3dca15fa820118 The only issue with FMA instructions is that there are _a lot_ of them (30 opcodes, each of which comes in up to 4 versions depending on VEX.W and VEX.L; a total of 96 possibilities). However, they can be implement with only 6 helpers, two for scalar operations and four for packed operations. (Scalar versions do not do any merging; they only affect the bottom 32 or 64 bits of the output operand. Therefore, there is no separate XMM and YMM of the scalar helpers). First, we can reduce the number of helpers to one third by passing four operands (one output and three inputs); the reordering of which operands go to the multiply and which go to the add is done in emit.c. Second, the different instructions also dispatch to the same softfloat function, so the flags for float32_muladd and float64_muladd are passed in the helper as int arguments, with a little extra complication to handle FMADDSUB and FMSUBADD. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> 2022-10-20T13:16:18+00:00 Paolo Bonzini 2022-10-19T11:22:06+00:00 urn:sha1:cf5ec6641ed456e2748b211b7bbf5103bfc93098 F16C only consists of two instructions, which are a bit peculiar nevertheless. First, they access only the low half of an YMM or XMM register for the packed-half operand; the exact size still depends on the VEX.L flag. This is similar to the existing avx_movx flag, but not exactly because avx_movx is hardcoded to affect operand 2. To this end I added a "ph" format name; it's possible to reuse this approach for the VPMOVSX and VPMOVZX instructions, though that would also require adding two more formats for the low-quarter and low-eighth of an operand. Second, VCVTPS2PH is somewhat weird because it *stores* the result of the instruction into memory rather than loading it. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> 2022-10-18T11:58:05+00:00 Paolo Bonzini 2022-09-20T16:00:03+00:00 urn:sha1:0339ddfa7562d835cca1dd468c2ad08b84a7abb5 Extracted from a patch by Paul Brook <paul@nowt.org>. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> 2022-10-06T10:53:40+00:00 Paolo Bonzini 2022-09-29T11:42:04+00:00 urn:sha1:15b273f8e6a4740768fba3878a346c82ef48a966 Further decoupling of tests/tcg from the main QEMU Makefile, and making the build more similar between the cross compiler case and the vetted container images. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220929114231.583801-25-alex.bennee@linaro.org> 2022-10-06T10:53:40+00:00 Paolo Bonzini 2022-09-29T11:42:03+00:00 urn:sha1:c6cf8a20521c7114893042cb7c75866bd07838ae Almost all invocations of run-test have either "$* on $(TARGET_NAME)" or "$< on $(TARGET_NAME)" as the last argument. So provide a default test name, while allowing an escape hatch for custom names. As an additional simplification, remove the need to do shell quoting. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220929114231.583801-24-alex.bennee@linaro.org> 2022-09-19T13:15:59+00:00 Paolo Bonzini 2022-09-11T13:04:54+00:00 urn:sha1:e121d7606bc9041619d8c6e0524a1ccdbbdd6547 The new testsuite is much more comprehensive, so remove the old one; it is also buggy (the pinsrw test uses incorrect constraints, with = instead of +, and the golden output for the fxsave tests differs depending on how the C library uses SSE and AVX instructions). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> 2022-09-19T13:15:59+00:00 Paolo Bonzini 2022-09-09T08:21:31+00:00 urn:sha1:e02907cc12df4765cc92f8b0c193a10c1841c82e Extend the support to memory operands, and skip MMX instructions that were introduced in SSE times, because they are now covered in test-mmx. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> 2022-09-19T13:14:40+00:00 Paolo Bonzini 2022-09-01T23:38:07+00:00 urn:sha1:fa7ce0b0282300c8c06a6c6857949168ec31a762 Adjust the test-avx.py generator to produce tests specifically for MMX and 3DNow. Using a separate generator introduces some code duplication, but is a simpler approach because of test-avx's extra complexity to support 3- and 4-operand AVX instructions. If needed, a common library can be introduced later. While at it, for consistency move all the -cpu max rules to the same place. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> 2022-09-18T07:17:41+00:00 Paolo Bonzini 2022-09-02T07:47:01+00:00 urn:sha1:4ce4a1a71452028960d641438bb5289cff410ae8 Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> 2022-09-06T07:04:25+00:00 Richard Henderson 2022-08-11T17:58:36+00:00 urn:sha1:d64655c2c35d967e9c496937885c511240204e76 We're about to start validating PAGE_EXEC, which means that we've got to put this code into a section that is both writable and executable. Note that this test did not run on hardware beforehand either. Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Tested-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>