<feed xmlns='http://www.w3.org/2005/Atom'>
<title>bwlp/qemu.git/tests/tcg/ppc64, branch master</title>
<subtitle>Experimental fork of QEMU with video encoding patches</subtitle>
<id>https://git.openslx.org/bwlp/qemu.git/atom/tests/tcg/ppc64?h=master</id>
<link rel='self' href='https://git.openslx.org/bwlp/qemu.git/atom/tests/tcg/ppc64?h=master'/>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/'/>
<updated>2022-10-06T10:53:40+00:00</updated>
<entry>
<title>tests/tcg: move compiler tests to Makefiles</title>
<updated>2022-10-06T10:53:40+00:00</updated>
<author>
<name>Paolo Bonzini</name>
</author>
<published>2022-09-29T11:42:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=15b273f8e6a4740768fba3878a346c82ef48a966'/>
<id>urn:sha1:15b273f8e6a4740768fba3878a346c82ef48a966</id>
<content type='text'>
Further decoupling of tests/tcg from the main QEMU Makefile, and making
the build more similar between the cross compiler case and the vetted
container images.

Signed-off-by: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
Signed-off-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Message-Id: &lt;20220929114231.583801-25-alex.bennee@linaro.org&gt;
</content>
</entry>
<entry>
<title>tests/tcg: unify ppc64 and ppc64le Makefiles</title>
<updated>2022-10-06T10:53:40+00:00</updated>
<author>
<name>Paolo Bonzini</name>
</author>
<published>2022-09-29T11:42:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=37b0dba45c4e44a02000a4170f25af0110f501d5'/>
<id>urn:sha1:37b0dba45c4e44a02000a4170f25af0110f501d5</id>
<content type='text'>
Make tests/tcg/ppc64le include tests/tcg/ppc64 instead of duplicating
the rules.  Because the ppc64le vpath includes tests/tcg/ppc64 but
not vice versa, the tests have to be moved from tests/tcg/ppc64le/
to tests/tcg/ppc64.

Signed-off-by: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
Signed-off-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Message-Id: &lt;20220929114231.583801-23-alex.bennee@linaro.org&gt;
</content>
</entry>
<entry>
<title>tests/tcg/ppc64: Add mffsce test</title>
<updated>2022-07-06T13:22:38+00:00</updated>
<author>
<name>Víctor Colombo</name>
</author>
<published>2022-06-29T16:29:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=7141a173c83414c4e1a4cda2d9ff1eaa6dccfee1'/>
<id>urn:sha1:7141a173c83414c4e1a4cda2d9ff1eaa6dccfee1</id>
<content type='text'>
Add mffsce test to check both the return value and the new fpscr
stored in the cpu.

Signed-off-by: Víctor Colombo &lt;victor.colombo@eldorado.org.br&gt;
Reviewed-by: Matheus Ferst &lt;matheus.ferst@eldorado.org.br&gt;
Message-Id: &lt;20220629162904.105060-8-victor.colombo@eldorado.org.br&gt;
Signed-off-by: Daniel Henrique Barboza &lt;danielhb413@gmail.com&gt;
</content>
</entry>
<entry>
<title>tests/tcg: add compiler test variables when using containers</title>
<updated>2022-04-20T15:04:20+00:00</updated>
<author>
<name>Paolo Bonzini</name>
</author>
<published>2022-04-19T09:10:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=f084839aba566b4a5199c461df4ba93b0e43580a'/>
<id>urn:sha1:f084839aba566b4a5199c461df4ba93b0e43580a</id>
<content type='text'>
Even for container-based cross compilation use $(CROSS_CC_HAS_*) variables.
This makes the TCG test makefiles oblivious of whether the compiler is
invoked through a container or not.

Signed-off-by: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
Reviewed-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Message-Id: &lt;20220401141326.1244422-10-pbonzini@redhat.com&gt;
Signed-off-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-Id: &lt;20220419091020.3008144-13-alex.bennee@linaro.org&gt;
</content>
</entry>
<entry>
<title>target/ppc: fix xxspltw for big endian hosts</title>
<updated>2022-03-14T14:57:17+00:00</updated>
<author>
<name>Matheus Ferst</name>
</author>
<published>2022-03-14T14:57:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=52d324ff13fcf97bc31f2e24803e366d330aa7cc'/>
<id>urn:sha1:52d324ff13fcf97bc31f2e24803e366d330aa7cc</id>
<content type='text'>
Fix a typo in the host endianness macro and add a simple test to detect
regressions.

Fixes: 9bb0048ec6f8 ("target/ppc: convert xxspltw to vector operations")
Signed-off-by: Matheus Ferst &lt;matheus.ferst@eldorado.org.br&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-Id: &lt;20220310172047.61094-1-matheus.ferst@eldorado.org.br&gt;
Signed-off-by: Cédric Le Goater &lt;clg@kaod.org&gt;
</content>
</entry>
<entry>
<title>tests/tcg: add vectorised sha512 versions</title>
<updated>2022-02-28T16:42:35+00:00</updated>
<author>
<name>Alex Bennée</name>
</author>
<published>2022-02-25T17:20:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=f8a4c6d728bc2427c5455379482f40ba8706a96f'/>
<id>urn:sha1:f8a4c6d728bc2427c5455379482f40ba8706a96f</id>
<content type='text'>
This builds vectorised versions of sha512 to exercise the vector code:

  - aarch64 (AdvSimd)
  - i386 (SSE)
  - s390x (MVX)
  - ppc64/ppc64le (power10 vectors)

Signed-off-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-Id: &lt;20220225172021.3493923-14-alex.bennee@linaro.org&gt;
</content>
</entry>
<entry>
<title>tests/tcg/ppc64: clean-up handling of byte-reverse</title>
<updated>2022-02-28T16:42:25+00:00</updated>
<author>
<name>Alex Bennée</name>
</author>
<published>2022-02-25T17:20:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=93f44896c9fa15d02d93eb396537c91c0efa8c11'/>
<id>urn:sha1:93f44896c9fa15d02d93eb396537c91c0efa8c11</id>
<content type='text'>
Rather than having an else leg for the missing compiler case we can
simply just not add the test - the same way as is done for ppc64le.
Also while we are at it fix up the compiler invocation.

Signed-off-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Message-Id: &lt;20220225172021.3493923-11-alex.bennee@linaro.org&gt;
</content>
</entry>
<entry>
<title>target/ppc: do not silence snan in xscvspdpn</title>
<updated>2022-01-04T06:55:34+00:00</updated>
<author>
<name>Matheus Ferst</name>
</author>
<published>2022-01-04T06:55:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=84ade98e87ea982ec6625ffd91058aaf443c206e'/>
<id>urn:sha1:84ade98e87ea982ec6625ffd91058aaf443c206e</id>
<content type='text'>
The non-signalling versions of VSX scalar convert to shorter/longer
precision insns doesn't silence SNaNs in the hardware. To better match
this behavior, use the non-arithmatic conversion of helper_todouble
instead of float32_to_float64. A test is added to prevent future
regressions.

Signed-off-by: Matheus Ferst &lt;matheus.ferst@eldorado.org.br&gt;
Message-Id: &lt;20211228120310.1957990-1-matheus.ferst@eldorado.org.br&gt;
Signed-off-by: Cédric Le Goater &lt;clg@kaod.org&gt;
</content>
</entry>
<entry>
<title>test/tcg/ppc64le: test mtfsf</title>
<updated>2021-12-17T16:57:13+00:00</updated>
<author>
<name>Lucas Mateus Castro (alqotel)</name>
</author>
<published>2021-12-17T16:57:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=00d38802513da6141a732ef7c3619bd0f8f01a8e'/>
<id>urn:sha1:00d38802513da6141a732ef7c3619bd0f8f01a8e</id>
<content type='text'>
Added tests for the mtfsf to check if FI bit of FPSCR is being set
and if exception calls are being made correctly.

Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Signed-off-by: Lucas Mateus Castro (alqotel) &lt;lucas.araujo@eldorado.org.br&gt;
Message-Id: &lt;20211201163808.440385-3-lucas.araujo@eldorado.org.br&gt;
Signed-off-by: Cédric Le Goater &lt;clg@kaod.org&gt;
</content>
</entry>
<entry>
<title>linux-user/ppc: Fix XER access in save/restore_user_regs</title>
<updated>2021-10-21T00:42:47+00:00</updated>
<author>
<name>Matheus Ferst</name>
</author>
<published>2021-10-14T22:32:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/bwlp/qemu.git/commit/?id=66c6b40aba13807506f20c7522f4930c9ffc76ce'/>
<id>urn:sha1:66c6b40aba13807506f20c7522f4930c9ffc76ce</id>
<content type='text'>
We should use cpu_read_xer/cpu_write_xer to save/restore the complete
register since some of its bits are in other fields of CPUPPCState. A
test is added to prevent future regressions.

Fixes: da91a00f191f ("target-ppc: Split out SO, OV, CA fields from XER")
Signed-off-by: Matheus Ferst &lt;matheus.ferst@eldorado.org.br&gt;
Message-Id: &lt;20211014223234.127012-2-matheus.ferst@eldorado.org.br&gt;
Reviewed-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Signed-off-by: David Gibson &lt;david@gibson.dropbear.id.au&gt;
</content>
</entry>
</feed>
