bwlp/qemu.git/tests/tcg/x86_64, branch spice_video_codecs

target/i386: fix cmpxchg with 32-bit register destination

2022-11-14T23:34:42+00:00

Unlike the memory case, where "the destination operand receives a write cycle without regard to the result of the comparison", rm must not be touched altogether if the write fails, including not zero-extending it on 64-bit processors. This is not how the movcond currently works, because it is always followed by a gen_op_mov_reg_v to rm. To fix it, introduce a new function that is similar to gen_op_mov_reg_v but writes to a TCG temporary. Considering that gen_extu(ot, oldv) is not needed in the memory case either, the two cases for register and memory destinations are different enough that one might as well fuse the two "if (mod == 3)" into one. So do that too. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/508 Signed-off-by: Paolo Bonzini [rth: Add a test case ] Signed-off-by: Richard Henderson

tests/tcg: clean up calls to run-test

2022-10-06T10:53:40+00:00

Almost all invocations of run-test have either "$* on $(TARGET_NAME)" or "$< on $(TARGET_NAME)" as the last argument. So provide a default test name, while allowing an escape hatch for custom names. As an additional simplification, remove the need to do shell quoting. Signed-off-by: Paolo Bonzini Signed-off-by: Alex Bennée Message-Id: <20220929114231.583801-24-alex.bennee@linaro.org>

tests/tcg: i386: add MMX and 3DNow! tests

2022-09-19T13:14:40+00:00

Adjust the test-avx.py generator to produce tests specifically for MMX and 3DNow. Using a separate generator introduces some code duplication, but is a simpler approach because of test-avx's extra complexity to support 3- and 4-operand AVX instructions. If needed, a common library can be introduced later. While at it, for consistency move all the -cpu max rules to the same place. Signed-off-by: Paolo Bonzini

target/i386: Make translator stop before the end of a page

2022-09-06T07:04:26+00:00

Right now translator stops right *after* the end of a page, which breaks reporting of fault locations when the last instruction of a multi-insn translation block crosses a page boundary. An implementation, like the one arm and s390x have, would require an i386 length disassembler, which is burdensome to maintain. Another alternative would be to single-step at the end of a guest page, but this may come with a performance impact. Fix by snapshotting disassembly state and restoring it after we figure out we crossed a page boundary. This includes rolling back cc_op updates and emitted ops. Signed-off-by: Ilya Leoshkevich Reviewed-by: Richard Henderson Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1143 Message-Id: <20220817150506.592862-4-iii@linux.ibm.com> [rth: Simplify end-of-insn cross-page checks.] Signed-off-by: Richard Henderson

tests/tcg: i386: add SSE tests

2022-09-01T18:16:33+00:00

Tests for correct operation of most x86-64 SSE instructions. It should cover all combinations of overlapping register and memory operands on a set of random-ish data. Results are bit-identical to an Intel i5-8500, with the exception of the RCPSS and RSQRT approximations where the real CPU gives less accurate results (the Intel spec allows relative errors up to 1.5 * 2^-12) Signed-off-by: Paul Brook Acked-by: Alex Bennée Message-Id: <20220424220204.2493824-42-paul@nowt.org> Signed-off-by: Paolo Bonzini

tests/tcg: x86_64: improve consistency with i386

2022-09-01T06:37:04+00:00

Include test-i386-bmi2, and specify manually the tests (only one for now) that need -cpu max. Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini

Fix 'writeable' typos

2022-06-08T18:38:47+00:00

We have about 30 instances of the typo/variant spelling 'writeable', and over 500 of the more common 'writable'. Standardize on the latter. Change produced with: sed -i -e 's/$[Ww][Rr][Ii][Tt]$[Ee]$[Aa][Bb][Ll][Ee]$/\1\2/g' $(git grep -il writeable) and then hand-undoing the instance in linux-headers/linux/kvm.h. Most of these changes are in comments or documentation; the exceptions are: * a local variable in accel/hvf/hvf-accel-ops.c * a local variable in accel/kvm/kvm-all.c * the PMCR_WRITABLE_MASK macro in target/arm/internals.h * the EPT_VIOLATION_GPA_WRITABLE macro in target/i386/hvf/vmcs.h (which is never used anywhere) * the AR_TYPE_WRITABLE_MASK macro in target/i386/hvf/vmx.h (which is never used anywhere) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Stefan Weil Message-id: 20220505095015.2714666-1-peter.maydell@linaro.org

tests/tcg: add missing reference files for float_convs

2022-04-20T15:04:20+00:00

We might as well include a reference file for i386/x86_64. I was going to include s390x as well but it's broken hence I raised: https://gitlab.com/qemu-project/qemu/-/issues/979. Signed-off-by: Alex Bennée Message-Id: <20220419091020.3008144-24-alex.bennee@linaro.org>

tests/tcg: add float_convd test

2022-04-20T15:04:20+00:00

This is a simple transliteration of the float_convs test but this time working with doubles. I'm used it to test the handling of vector registers in gdbstub but wasn't able to find a non-ugly way to automate it. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20220419091020.3008144-23-alex.bennee@linaro.org>

tests/tcg: remove duplicate sha512-sse case

2022-04-20T15:04:20+00:00

We already generate the sha512-sse case in the i386 makefile which works for both i386 and x86_64. Signed-off-by: Alex Bennée Fixes: f8a4c6d728 ("tests/tcg: add vectorised sha512 versions") Reviewed-by: Richard Henderson Message-Id: <20220419091020.3008144-22-alex.bennee@linaro.org>