bwlp/qemu.git/tests/tcg/xtensa, branch master

tests/tcg/xtensa: fix vectors and checks in timer test

2022-05-06T22:27:40+00:00

Timer test assumes that timer 0 IRQ has level 1 and other timers have higher level IRQs. This assumption is not correct and the levels may be arbitrary. Fix that assumption by providing TIMER*_VECTOR macro and using it for vector selection and by making the check for the timer exception cause conditional. Signed-off-by: Max Filippov

tests/tcg/xtensa: enable mmu tests for MMUv3

2022-05-06T22:27:40+00:00

MMU test suite is disabled for cores that have spanning TLB way, i.e. for all MMUv3 cores. Instead of disabling it make testing region virtual addresses explicit and invalidate TLB mappings for entries that conflict with the test. Signed-off-by: Max Filippov

tests/tcg/xtensa: enable autorefill phys_mem tests for MMUv3

2022-05-06T22:27:40+00:00

Autorefill tests in the phys_mem test suite are disabled for cores that have spanning TLB way, i.e. for all MMUv3 cores. Instead of disabling it invalidate TLB mappings for entries that conflict with the test. Signed-off-by: Max Filippov

tests/tcg/xtensa: remove dependency on the loop option

2022-05-06T22:27:40+00:00

xtensa core may not have the loop option, but still have timers. Don't use loop opcode in the timer test. Signed-off-by: Max Filippov

tests/tcg/xtensa: fix watchpoint test

2022-05-06T22:27:40+00:00

xtensa core may have only one set of DBREAKA/DBREAKC registers. Don't hardcode register numbers in the test as 0 and 1, use macros that only index valid DBREAK* registers. Signed-off-by: Max Filippov

tests/tcg/xtensa: restore vecbase SR after test

2022-05-06T22:27:40+00:00

Writing garbage into the vecbase SR results in hang in the subsequent tests that expect to raise an exception. Restore vecbase SR to its reset value after the test. Signed-off-by: Max Filippov

tests/tcg/xtensa: fix build for cores without windowed registers

2022-05-06T22:27:40+00:00

Don't try to initialize windowbase/windowstart in crt.S if they don't exist. Signed-off-by: Max Filippov

Replace TARGET_WORDS_BIGENDIAN

2022-04-06T08:50:37+00:00

Convert the TARGET_WORDS_BIGENDIAN macro, similarly to what was done with HOST_BIG_ENDIAN. The new TARGET_BIG_ENDIAN macro is either 0 or 1, and thus should always be defined to prevent misuse. Signed-off-by: Marc-André Lureau Suggested-by: Halil Pasic Reviewed-by: Richard Henderson Message-Id: <20220323155743.1585078-8-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini

target/xtensa: clean up unaligned access

2021-05-20T20:02:58+00:00

Xtensa cores may or may not have hardware support for unaligned memory access. Remove TARGET_ALIGNED_ONLY=y from all xtensa configurations and pass MO_ALIGN in memory access flags for all operations that would raise an exception. Simplify use of gen_load_store_alignment by passing access size and alignment requirements in single parameter. Drop condition from xtensa_cpu_do_unaligned_access and replace it with assertion. Add a test. Suggested-by: Philippe Mathieu-Daudé Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Max Filippov

tests/tcg/xtensa: add DFP0 arithmetic tests

2020-08-21T19:48:16+00:00

Add test for basic double precision opcode properties. Signed-off-by: Max Filippov