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| author | Peter Maydell | 2017-01-27 16:20:24 +0100 |
|---|---|---|
| committer | Peter Maydell | 2017-01-27 16:29:08 +0100 |
| commit | 056f43df9168413f304500b69c33158d66efb7cf (patch) | |
| tree | 4bc0df0c4f89b55e38504b9225783a954246e11e | |
| parent | armv7m: FAULTMASK should be 0 on reset (diff) | |
| download | qemu-056f43df9168413f304500b69c33158d66efb7cf.tar.gz qemu-056f43df9168413f304500b69c33158d66efb7cf.tar.xz qemu-056f43df9168413f304500b69c33158d66efb7cf.zip | |
armv7m: R14 should reset to 0xffffffff
For M profile (unlike A profile) the reset value of R14 is specified
as 0xffffffff. (The rationale is that this is an illegal exception
return value, so if guest code tries to return to it it will result
in a helpful exception.)
Registers r0 to r12 and the flags are architecturally UNKNOWN on
reset, so we leave those at zero.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 1485285380-10565-11-git-send-email-peter.maydell@linaro.org
| -rw-r--r-- | target/arm/cpu.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0814f73462..e9f10f7747 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -196,6 +196,9 @@ static void arm_cpu_reset(CPUState *s) */ env->v7m.ccr = R_V7M_CCR_STKALIGN_MASK; + /* Unlike A/R profile, M profile defines the reset LR value */ + env->regs[14] = 0xffffffff; + /* Load the initial SP and PC from the vector table at address 0 */ rom = rom_ptr(0); if (rom) { |