diff options
| author | Jason Wang | 2012-03-22 11:01:50 +0100 |
|---|---|---|
| committer | Michael S. Tsirkin | 2012-04-25 09:53:48 +0200 |
| commit | 17fbbb0b3d0b09f07d288991248c81f441bf6941 (patch) | |
| tree | a89efb5a31522621472291ebd6937f1a68fd314f | |
| parent | e1000: introduce bits of PHY control register (diff) | |
| download | qemu-17fbbb0b3d0b09f07d288991248c81f441bf6941.tar.gz qemu-17fbbb0b3d0b09f07d288991248c81f441bf6941.tar.xz qemu-17fbbb0b3d0b09f07d288991248c81f441bf6941.zip | |
e1000: conditionally raise irq at the end of MDI cycle
According to the spec:
"When set to 1b by software, it causes an Interrupt to be
asserted to indicate the end of an MDI cycle."
We need check the Interrupt Enable bit and raise irq only when it is
set.
Signed-off-by: Jason Wang <jasowang@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| -rw-r--r-- | hw/e1000.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/hw/e1000.c b/hw/e1000.c index dd067680c9..4e787bc2cf 100644 --- a/hw/e1000.c +++ b/hw/e1000.c @@ -274,7 +274,10 @@ set_mdic(E1000State *s, int index, uint32_t val) s->phy_reg[addr] = data; } s->mac_reg[MDIC] = val | E1000_MDIC_READY; - set_ics(s, 0, E1000_ICR_MDAC); + + if (val & E1000_MDIC_INT_EN) { + set_ics(s, 0, E1000_ICR_MDAC); + } } static uint32_t |