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| author | Richard Henderson | 2018-01-07 01:02:27 +0100 |
|---|---|---|
| committer | Richard Henderson | 2018-01-31 14:30:50 +0100 |
| commit | 7b93dab51e929d7c2878cb5ad92b4419e3318e73 (patch) | |
| tree | 82e1181a5bae861b3584ec076488284093d30c84 | |
| parent | target/hppa: Implement STWA (diff) | |
| download | qemu-7b93dab51e929d7c2878cb5ad92b4419e3318e73.tar.gz qemu-7b93dab51e929d7c2878cb5ad92b4419e3318e73.tar.xz qemu-7b93dab51e929d7c2878cb5ad92b4419e3318e73.zip | |
target/hppa: Enable MTTCG
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rwxr-xr-x | configure | 1 | ||||
| -rw-r--r-- | target/hppa/cpu.h | 6 |
2 files changed, 7 insertions, 0 deletions
@@ -6555,6 +6555,7 @@ case "$target_name" in cris) ;; hppa) + mttcg="yes" ;; lm32) ;; diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 70af823a15..7640c81221 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -42,6 +42,12 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #endif +/* PA-RISC 1.x processors have a strong memory model. */ +/* ??? While we do not yet implement PA-RISC 2.0, those processors have + a weak memory model, but with TLB bits that force ordering on a per-page + basis. It's probably easier to fall back to a strong memory model. */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #define CPUArchState struct CPUHPPAState #include "exec/cpu-defs.h" |